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Merge branch 'vtr_master'
Signed-off-by: Ethan Rogers <[email protected]>
2 parents 834f4ab + 45bf4c9 commit f6c1dca

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‎.github/kokoro/continuous/nightly.cfg

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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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regex: "**/*.out.gz"
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regex: "**/vpr_stdout.log.gz"
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regex: "**/parse_results.txt.gz"
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regex: "**/qor_results.txt.gz"
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regex: "**/pack.log.gz"
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regex: "**/place.log.gz"
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regex: "**/route.log.gz"
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regex: "**/*_qor.csv.gz"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}

‎.github/kokoro/continuous/odin_strong.cfg

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# Format: //devtools/kokoro/config/proto/build.proto
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build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
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# 12 hours
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timeout_mins: 720
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action {
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define_artifacts {
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# File types
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regex: "**/*.out"
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regex: "**/vpr_stdout.log"
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regex: "**/parse_results.txt"
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regex: "**/qor_results.txt"
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regex: "**/pack.log"
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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}
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env_vars {
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key: "KOKORO_TYPE"
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value: "continuous"
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}
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env_vars {
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key: "KOKORO_DIR"
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value: "vtr-verilog-to-routing"
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}
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env_vars {
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key: "VTR_DIR"
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value: "vtr-verilog-to-routing"
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}
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#Use default build configuration
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env_vars {
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key: "VTR_CMAKE_PARAMS"
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value: ""
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}
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env_vars {
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key: "VTR_TEST"
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value: "odin_reg_strong"
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}
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#Options for run_reg_test.py
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# -show_failures: show tool failures in main log output
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env_vars {
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key: "VTR_TEST_OPTIONS"
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value: "-show_failures"
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}
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env_vars {
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key: "NUM_CORES"
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value: "3"
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}

‎.github/kokoro/continuous/strong.cfg

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@@ -16,6 +16,14 @@ action {
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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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regex: "**/*.out.gz"
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regex: "**/vpr_stdout.log.gz"
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regex: "**/parse_results.txt.gz"
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regex: "**/qor_results.txt.gz"
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regex: "**/pack.log.gz"
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regex: "**/place.log.gz"
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regex: "**/route.log.gz"
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regex: "**/*_qor.csv.gz"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}

‎.github/kokoro/continuous/strong_sanitized.cfg

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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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regex: "**/*.out.gz"
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regex: "**/vpr_stdout.log.gz"
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regex: "**/parse_results.txt.gz"
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regex: "**/qor_results.txt.gz"
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regex: "**/pack.log.gz"
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regex: "**/place.log.gz"
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regex: "**/route.log.gz"
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regex: "**/*_qor.csv.gz"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}

‎.github/kokoro/continuous/weekly.cfg

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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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regex: "**/*.out.gz"
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regex: "**/vpr_stdout.log.gz"
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regex: "**/parse_results.txt.gz"
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regex: "**/qor_results.txt.gz"
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regex: "**/pack.log.gz"
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regex: "**/place.log.gz"
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regex: "**/route.log.gz"
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regex: "**/*_qor.csv.gz"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}

‎.github/kokoro/presubmit/odin_strong.cfg

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# Format: //devtools/kokoro/config/proto/build.proto
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build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
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# 12 hours
6+
timeout_mins: 720
7+
8+
action {
9+
define_artifacts {
10+
# File types
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regex: "**/*.out"
12+
regex: "**/vpr_stdout.log"
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regex: "**/parse_results.txt"
14+
regex: "**/qor_results.txt"
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regex: "**/pack.log"
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regex: "**/place.log"
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regex: "**/route.log"
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regex: "**/*_qor.csv"
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strip_prefix: "github/vtr-verilog-to-routing/"
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}
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}
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env_vars {
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key: "KOKORO_TYPE"
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value: "presubmit"
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}
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env_vars {
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key: "KOKORO_DIR"
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value: "vtr-verilog-to-routing"
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}
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env_vars {
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key: "VTR_DIR"
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value: "vtr-verilog-to-routing"
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}
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#Use default build configuration
39+
env_vars {
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key: "VTR_CMAKE_PARAMS"
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value: ""
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}
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env_vars {
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key: "VTR_TEST"
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value: "odin_reg_strong"
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}
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#Options for run_reg_test.py
50+
# -show_failures: show tool failures in main log output
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env_vars {
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key: "VTR_TEST_OPTIONS"
53+
value: "-show_failures"
54+
}
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env_vars {
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key: "NUM_CORES"
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value: "3"
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}

‎.github/kokoro/run-vtr.sh

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@@ -16,7 +16,7 @@ source $SCRIPT_DIR/steps/hostinfo.sh
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# Output git information
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source $SCRIPT_DIR/steps/git.sh
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19-
if [ $VTR_TEST == "vtr_reg_strong" ]; then
19+
if [ $VTR_TEST == "vtr_reg_strong" ] || [ $VTR_TEST == "odin_reg_strong" ]; then
2020
source $SCRIPT_DIR/steps/vtr-min-setup.sh
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else
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source $SCRIPT_DIR/steps/vtr-full-setup.sh

‎.github/kokoro/steps/vtr-full-setup.sh

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make get_titan_benchmarks
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make get_ispd_benchmarks
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make get_symbiflow_benchmarks
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dev/upgrade_vtr_archs.sh
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# Symbiflow archs do not require update
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make get_symbiflow_benchmarks

‎.github/workflows/test.yml

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./.github/travis/setup.sh
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ODINII:
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name: 'ODIN-II Micro Tests'
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name: 'ODIN-II Basic Tests'
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runs-on: ubuntu-18.04
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steps:
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source .github/travis/common.sh
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./.github/travis/setup.sh
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./.github/travis/build.sh
222-
./run_reg_test.py odin_reg_micro -show_failures -j2
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./run_reg_test.py odin_reg_basic -show_failures -j2
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./.github/travis/setup.sh
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‎ODIN_II/SRC/ast_elaborate.cpp

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@@ -1813,8 +1813,11 @@ ast_node_t* reduce_expressions(ast_node_t* node, sc_hierarchy* local_ref, long*
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18141814
vtr::free(max_size);
18151815

1816-
/* cast to unsigned if necessary */
1817-
if (node_is_constant(node->children[1])) {
1816+
/*
1817+
* cast to unsigned if necessary
1818+
* Concatenate results are unsigned, regardless of the operands. IEEE.1364-2005 pp.65
1819+
*/
1820+
if (node->children[0]->type != CONCATENATE && node_is_constant(node->children[1])) {
18181821
char* id = NULL;
18191822
if (node->children[0]->type == IDENTIFIERS) {
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id = node->children[0]->types.identifier;

‎ODIN_II/SRC/netlist_create_from_ast.cpp

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54185418
return return_list;
54195419
}
54205420

5421+
/**
5422+
* --------------------------------------------------------------------------
5423+
* (function: reorder_connections_from_name)
5424+
*
5425+
* @brief reorder the instantiated instance ports based on
5426+
* the order of the main item(module, function or task)
5427+
*
5428+
* @param instance_node_list including the list of the main item ports
5429+
* @param instantiated_instance_list including the list of the instantiated instance ports
5430+
* @param ids the type of the main item or instance (module, function or task)
5431+
*--------------------------------------------------------------------------*/
54215432
void reorder_connections_from_name(ast_node_t* instance_node_list, ast_node_t* instantiated_instance_list, ids type) {
54225433
int i, j;
54235434
bool has_matched;
5424-
int* arr_index = new int[instantiated_instance_list->num_children];
54255435
int start_index = type == FUNCTION ? 1 : 0;
5436+
int* arr_index = (int*)vtr::malloc(instantiated_instance_list->num_children * sizeof(int));
5437+
memset(arr_index, -1, (instantiated_instance_list->num_children) * sizeof(int));
54265438

5439+
// find the mismatch and store the right index for each item in arr_index
54275440
for (i = start_index; i < instantiated_instance_list->num_children; i++) {
54285441
has_matched = false;
54295442
arr_index[i] = -1;
@@ -5445,17 +5458,27 @@ void reorder_connections_from_name(ast_node_t* instance_node_list, ast_node_t* i
54455458
}
54465459
}
54475460

5461+
// keep the reordered instantiated instance port in an array to swap them later
5462+
ast_node_t** swapping_children = (ast_node_t**)vtr::calloc(instantiated_instance_list->num_children, sizeof(ast_node_t*));
54485463
for (i = start_index; i < instantiated_instance_list->num_children; i++) {
54495464
if (arr_index[i] != -1) {
5450-
ast_node_t* temp = instantiated_instance_list->children[arr_index[i]];
5451-
instantiated_instance_list->children[arr_index[i]] = instantiated_instance_list->children[i];
5452-
instantiated_instance_list->children[i] = temp;
5453-
arr_index[arr_index[i]] = -1;
5465+
swapping_children[arr_index[i]] = instantiated_instance_list->children[i];
54545466
}
54555467
}
54565468

5457-
delete[] arr_index;
5469+
// make instantiated instance ports ordered by swapping them using reordered indexes
5470+
for (i = start_index; i < instantiated_instance_list->num_children; i++) {
5471+
instantiated_instance_list->children[i] = (swapping_children[i]) ? swapping_children[i]
5472+
: instantiated_instance_list->children[i];
5473+
swapping_children[i] = NULL;
5474+
}
5475+
5476+
// free the allocated memory
5477+
if (swapping_children)
5478+
vtr::free(swapping_children);
5479+
vtr::free(arr_index);
54585480
}
5481+
54595482
/*--------------------------------------------------------------------------
54605483
* Resolves top module parameters and defparams defined by it's own parameters as those parameters cannot be overriden
54615484
* Technically the top module parameters can be overriden by defparams in a seperate module however that cannot be supported until

‎ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf

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regression_test/benchmark/task/FIR
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regression_test/benchmark/task/micro
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regression_test/benchmark/suite/complex_synthesis_suite
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regression_test/benchmark/suite/vtr_multiclock_suite

‎ODIN_II/regression_test/benchmark/suite/vtr_multiclock_suite/task_list.conf

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vtr::vtr_reg_multiclock

‎ODIN_II/regression_test/benchmark/task/syntax/simulation_result.json

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"Estimated LUTs": 22,
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"Total Node": 31
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},
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"syntax/unordered_ports/k6_frac_N10_frac_chain_mem32K_40nm": {
2815+
"test_name": "syntax/unordered_ports/k6_frac_N10_frac_chain_mem32K_40nm",
2816+
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
2817+
"blif": "unordered_ports.blif",
2818+
"max_rss(MiB)": 8.9,
2819+
"exec_time(ms)": 13.3,
2820+
"simulation_time(ms)": 0.6,
2821+
"test_coverage(%)": 100,
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"Pi": 4,
2823+
"Po": 4,
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"logic element": 6,
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"generic logic size": 4,
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"Longest Path": 4,
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"Average Path": 4,
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"Estimated LUTs": 6,
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"Total Node": 6
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},
2831+
"syntax/unordered_ports/no_arch": {
2832+
"test_name": "syntax/unordered_ports/no_arch",
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"blif": "unordered_ports.blif",
2834+
"max_rss(MiB)": 8,
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"exec_time(ms)": 2,
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"simulation_time(ms)": 0.5,
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"test_coverage(%)": 100,
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"Pi": 4,
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"Po": 4,
2840+
"logic element": 6,
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"Longest Path": 4,
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"Average Path": 4,
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"Estimated LUTs": 6,
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"Total Node": 6
2845+
},
28142846
"DEFAULT": {
28152847
"test_name": "n/a",
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"architecture": "n/a",

‎ODIN_II/regression_test/benchmark/task/syntax/synthesis_result.json

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"Estimated LUTs": 14,
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"Total Node": 23
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},
3345+
"syntax/unordered_ports/k6_frac_N10_frac_chain_mem32K_40nm": {
3346+
"test_name": "syntax/unordered_ports/k6_frac_N10_frac_chain_mem32K_40nm",
3347+
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
3348+
"verilog": "unordered_ports.v",
3349+
"max_rss(MiB)": 6.1,
3350+
"exec_time(ms)": 12.3,
3351+
"synthesis_time(ms)": 1,
3352+
"Pi": 4,
3353+
"Po": 4,
3354+
"logic element": 2,
3355+
"Adder": 0,
3356+
"Multiplier": 0,
3357+
"Memory": 0,
3358+
"generic logic size": 4,
3359+
"Longest Path": 3,
3360+
"Average Path": 2,
3361+
"Estimated LUTs": 2,
3362+
"Total Node": 2
3363+
},
3364+
"syntax/unordered_ports/no_arch": {
3365+
"test_name": "syntax/unordered_ports/no_arch",
3366+
"verilog": "unordered_ports.v",
3367+
"max_rss(MiB)": 4.4,
3368+
"exec_time(ms)": 1.1,
3369+
"synthesis_time(ms)": 0.9,
3370+
"Pi": 4,
3371+
"Po": 4,
3372+
"logic element": 2,
3373+
"Longest Path": 3,
3374+
"Average Path": 2,
3375+
"Estimated LUTs": 2,
3376+
"Total Node": 2
3377+
},
33453378
"DEFAULT": {
33463379
"test_name": "n/a",
33473380
"architecture": "n/a",

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