Modified the code a bit to understand how an API may be put into place.

Signed-off-by: Ethan Rogers <[email protected]>

Author: ethanroj23

Makefile

@@ -17,7 +17,7 @@
 #    release		#Build with compiler optimization
 #    debug			#Build with debug info and no compiler optimization
 #    strict			#Build VPR with warnings treated as errors
-BUILD_TYPE ?= release
+BUILD_TYPE ?= debug
 
 #Convert to lower case for consistency
 BUILD_TYPE := $(shell echo $(BUILD_TYPE) | tr '[:upper:]' '[:lower:]')
@@ -105,7 +105,7 @@ endif #BUILD_TYPE
 	#Final build
 	#
 	@echo "Building target(s): $(MAKECMDGOALS)"
-	@+$(MAKE) -C $(BUILD_DIR) $(MAKECMDGOALS)
+	@+$(MAKE) -C  $(BUILD_DIR) $(MAKECMDGOALS) CXXFLAGS="-g"
 endif #clean
 endif #distclean
 

vpr/src/place/timing_place_lookup.cpp

@@ -351,13 +351,13 @@ static float route_connection_delay(
         VTR_ASSERT(driver_ptc != OPEN);
 
         int source_rr_node = get_rr_node_index(device_ctx.rr_node_indices, source_x, source_y, SOURCE, driver_ptc);
-
         VTR_ASSERT(source_rr_node != OPEN);
 
         for (int sink_ptc : best_sink_ptcs) {
             VTR_ASSERT(sink_ptc != OPEN);
-
+        
             int sink_rr_node = get_rr_node_index(device_ctx.rr_node_indices, sink_x, sink_y, SINK, sink_ptc);
+            //printf("sink:%d", sink_rr_node);
 
             VTR_ASSERT(sink_rr_node != OPEN);
 

vpr/src/route/gen/rr_graph_uxsdcxx.h

@@ -322,6 +322,7 @@ bool try_timing_driven_route_tmpl(const t_router_opts& router_opts,
      */
     bool routing_is_successful = false;
     WirelengthInfo wirelength_info;
+    //ESR API Access (get total number of nodes)
     OveruseInfo overuse_info(device_ctx.rr_nodes.size());
     tatum::TimingPathInfo critical_path;
     int itry; //Routing iteration number
@@ -545,6 +546,26 @@ bool try_timing_driven_route_tmpl(const t_router_opts& router_opts,
                 best_clb_opins_used_locally = router_ctx.clb_opins_used_locally;
 
                 routing_is_successful = true;
+                
+                // ESR print out path for a given net
+                for (auto net_id : cluster_ctx.clb_nlist.nets()) {
+                    auto current_node = best_routing[net_id].head;
+                    std::cout << "-------\n";
+                    while (current_node != nullptr){
+                        auto current_type = device_ctx.rr_nodes[current_node->index].type_string();
+                        auto xlow = device_ctx.rr_nodes[current_node->index].xlow();
+                        auto xhigh = device_ctx.rr_nodes[current_node->index].xhigh();
+                        auto ylow = device_ctx.rr_nodes[current_node->index].ylow();
+                        auto yhigh = device_ctx.rr_nodes[current_node->index].yhigh();
+                        if ((xlow == xhigh) && (ylow == yhigh)){
+                            printf("Node: %d %s (%d,%d) \n", current_node->index, current_type, xlow, ylow);
+                        }
+                        else{
+                            printf("Node: %d %s (%d,%d) to (%d,%d) \n", current_node->index, current_type, xlow,ylow,xhigh,yhigh);
+                        }
+                        current_node = current_node->next;
+                    }
+                }
 
                 //Update best metrics
                 if (timing_info) {
@@ -786,7 +807,7 @@ bool try_timing_driven_route_tmpl(const t_router_opts& router_opts,
             VTR_LOG("Critical path: %g ns\n", 1e9 * best_routing_metrics.critical_path.delay());
         }
 
-        VTR_LOG("Successfully routed after %d routing iterations.\n", itry);
+        VTR_LOG("#ESR timing Successfully routed after %d routing iterations.\n", itry);
     } else {
         VTR_LOG("Routing failed.\n");
 
@@ -1158,11 +1179,12 @@ bool timing_driven_route_net(ConnectionRouter& router,
     if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) {
         for (unsigned ipin = 1; ipin < cluster_ctx.clb_nlist.net_pins(net_id).size(); ++ipin) {
             if (net_delay[ipin] == 0) { // should be SOURCE->OPIN->IPIN->SINK
+                //ESR API Access (get type of node)
                 VTR_ASSERT(device_ctx.rr_nodes[rt_node_of_sink[ipin]->parent_node->parent_node->inode].type() == OPIN);
             }
         }
     }
-
+    //ESR API Access (get capacity of node)
     VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_nodes[rt_root->inode].capacity(), "SOURCE should never be congested");
 
     // route tree is not kept persistent since building it from the traceback the next iteration takes almost 0 time
@@ -1519,6 +1541,7 @@ void disable_expansion_and_remove_sink_from_route_tree_nodes(t_rt_node* rt_node)
 
     while (linked_rt_edge != nullptr) {
         child_node = linked_rt_edge->child;
+        //ESR API Access (get type of node)
         if (device_ctx.rr_nodes[child_node->inode].type() == SINK) {
             VTR_LOGV_DEBUG(f_router_debug,
                            "Removing sink %d from route tree\n", child_node->inode);
@@ -1607,6 +1630,7 @@ static bool should_route_net(ClusterNetId net_id, CBRR& connections_inf, bool if
     for (;;) {
         int inode = tptr->index;
         int occ = route_ctx.rr_node_route_inf[inode].occ();
+        //ESR API Access (get capacity of node)
         int capacity = device_ctx.rr_nodes[inode].capacity();
 
         if (occ > capacity) {
@@ -1663,6 +1687,8 @@ static size_t calculate_wirelength_available() {
     auto& device_ctx = g_vpr_ctx.device();
 
     size_t available_wirelength = 0;
+    //ESR API Access (Get total number of nodes, type, and width/height of nodes, and available wirelength)
+    // But really what's happening is that this for loop iterates over every node and determines the available wirelength
     for (size_t i = 0; i < device_ctx.rr_nodes.size(); ++i) {
         if (device_ctx.rr_nodes[i].type() == CHANX || device_ctx.rr_nodes[i].type() == CHANY) {
             size_t length_x = device_ctx.rr_nodes[i].xhigh() - device_ctx.rr_nodes[i].xlow();
@@ -1940,6 +1966,7 @@ static t_bb calc_current_bb(const t_trace* head) {
     bb.ymax = 0;
 
     for (const t_trace* elem = head; elem != nullptr; elem = elem->next) {
+        //ESR API Access (Direct access a node)
         const t_rr_node& node = device_ctx.rr_nodes[elem->index];
         //The router interprets RR nodes which cross the boundary as being
         //'within' of the BB. Only those which are *strictly* out side the

vpr/src/route/route_timing.cpp

@@ -80,7 +80,7 @@ bool alloc_route_tree_timing_structs(bool exists_ok) {
     /* Allocates any structures needed to build the routing trees. */
 
     auto& device_ctx = g_vpr_ctx.device();
-
+    //ESR API Access (Get total number of nodes)
     bool route_tree_structs_are_allocated = (rr_node_to_rt_node.size() == size_t(device_ctx.rr_nodes.size())
                                              || rt_node_free_list != nullptr);
     if (route_tree_structs_are_allocated) {
@@ -196,6 +196,7 @@ t_rt_node* init_route_tree_to_source(ClusterNetId inet) {
 
     rt_root->inode = inode;
     rt_root->net_pin_index = OPEN;
+    //ESR API Access (get Capacitance and Resistance [4 times])
     rt_root->C_downstream = device_ctx.rr_nodes[inode].C();
     rt_root->R_upstream = device_ctx.rr_nodes[inode].R();
     rt_root->Tdel = 0.5 * device_ctx.rr_nodes[inode].R() * device_ctx.rr_nodes[inode].C();
@@ -264,7 +265,8 @@ t_rt_node* update_route_tree(t_heap* hptr, int target_net_pin_index, SpatialRout
 void add_route_tree_to_rr_node_lookup(t_rt_node* node) {
     if (node) {
         auto& device_ctx = g_vpr_ctx.device();
-        if (device_ctx.rr_nodes[node->inode].type() == SINK) {
+        //ESR API Access (get type of node)
+        if (device_ctx.rr_nodes[node->inode].type() == SINK) { //ESR keep iterating until you get to a sink?
             VTR_ASSERT(rr_node_to_rt_node[node->inode] == nullptr || rr_node_to_rt_node[node->inode]->inode == node->inode);
         } else {
             VTR_ASSERT(rr_node_to_rt_node[node->inode] == nullptr || rr_node_to_rt_node[node->inode] == node);
@@ -318,6 +320,7 @@ add_subtree_to_route_tree(t_heap* hptr, int target_net_pin_index, t_rt_node** si
     std::unordered_set<int> all_visited;         //does not include sink
     inode = hptr->prev_node();
     RREdgeId edge = hptr->prev_edge();
+    //ESR API Access (get the switch for the edge)
     short iswitch = device_ctx.rr_nodes.edge_switch(edge);
 
     /* For all "new" nodes in the main path */
@@ -348,6 +351,7 @@ add_subtree_to_route_tree(t_heap* hptr, int target_net_pin_index, t_rt_node** si
 
         rr_node_to_rt_node[inode] = rt_node;
 
+        //ESR API Access (get type of node)
         if (device_ctx.rr_nodes[inode].type() == IPIN) {
             rt_node->re_expand = false;
         } else {
@@ -357,6 +361,7 @@ add_subtree_to_route_tree(t_heap* hptr, int target_net_pin_index, t_rt_node** si
         downstream_rt_node = rt_node;
         edge = route_ctx.rr_node_route_inf[inode].prev_edge;
         inode = route_ctx.rr_node_route_inf[inode].prev_node;
+        //ESR API Access (get type of edge)
         iswitch = device_ctx.rr_nodes.edge_switch(edge);
     }
 
@@ -405,7 +410,7 @@ static t_rt_node* add_non_configurable_to_route_tree(const int rr_node, const bo
                 rt_node->u.child_list = nullptr;
                 rt_node->inode = rr_node;
                 rt_node->net_pin_index = OPEN;
-
+                //ESR API Access (get type of node)
                 if (device_ctx.rr_nodes[rr_node].type() == IPIN) {
                     rt_node->re_expand = false;
                 } else {
@@ -415,7 +420,7 @@ static t_rt_node* add_non_configurable_to_route_tree(const int rr_node, const bo
                 VTR_ASSERT(rt_node->inode == rr_node);
             }
         }
-
+        //ESR API Access (get non configurable edges, configurable edges, and edge_sink_node)
         for (int iedge : device_ctx.rr_nodes[rr_node].non_configurable_edges()) {
             //Recursive case: expand children
             VTR_ASSERT(!device_ctx.rr_nodes[rr_node].edge_is_configurable(iedge));
@@ -426,7 +431,7 @@ static t_rt_node* add_non_configurable_to_route_tree(const int rr_node, const bo
             t_rt_node* child_rt_node = add_non_configurable_to_route_tree(to_rr_node, true, visited);
 
             if (!child_rt_node) continue;
-
+            //ESR API Access (get type of switch)
             int iswitch = device_ctx.rr_nodes[rr_node].edge_switch(iedge);
 
             //Create the edge
@@ -472,6 +477,7 @@ void load_new_subtree_R_upstream(t_rt_node* rt_node) {
         }
         R_upstream += device_ctx.rr_switch_inf[iswitch].R; //Parent switch R
     }
+    //ESR API Access (get current node Resistance)
     R_upstream += device_ctx.rr_nodes[inode].R(); //Current node R
 
     rt_node->R_upstream = R_upstream;
@@ -487,7 +493,7 @@ float load_new_subtree_C_downstream(t_rt_node* rt_node) {
 
     if (rt_node) {
         auto& device_ctx = g_vpr_ctx.device();
-
+        //ESR API Access (get node's Capacitance)
         C_downstream += device_ctx.rr_nodes[rt_node->inode].C();
         for (t_linked_rt_edge* edge = rt_node->u.child_list; edge != nullptr; edge = edge->next) {
             /*Similar to net_delay.cpp, this for loop traverses a rc subtree, whose edges represent enabled switches.
@@ -580,7 +586,7 @@ void load_route_tree_Tdel(t_rt_node* subtree_rt_root, float Tarrival) {
     /* Assuming the downstream connections are, on average, connected halfway
      * along a wire segment's length.  See discussion in net_delay.c if you want
      * to change this.                                                           */
-
+    //ESR API Access (get node's Resistance)
     Tdel = Tarrival + 0.5 * subtree_rt_root->C_downstream * device_ctx.rr_nodes[inode].R();
     subtree_rt_root->Tdel = Tdel;
 
@@ -688,6 +694,7 @@ void print_route_tree(const t_rt_node* rt_node, int depth) {
     }
 
     auto& device_ctx = g_vpr_ctx.device();
+    //ESR API Access (get node's type string)
     VTR_LOG("%srt_node: %d (%s) \t ipin: %d \t R: %g \t C: %g \t delay: %g",
             indent.c_str(), rt_node->inode, device_ctx.rr_nodes[rt_node->inode].type_string(), rt_node->net_pin_index, rt_node->R_upstream, rt_node->C_downstream, rt_node->Tdel);
 
@@ -699,7 +706,7 @@ void print_route_tree(const t_rt_node* rt_node, int depth) {
     }
 
     auto& route_ctx = g_vpr_ctx.routing();
-
+    //ESR API Access (Get node's capacity)
     if (route_ctx.rr_node_route_inf[rt_node->inode].occ() > device_ctx.rr_nodes[rt_node->inode].capacity()) {
         VTR_LOG(" x");
     }
@@ -801,6 +808,7 @@ static t_trace* traceback_to_route_tree_branch(t_trace* trace,
         // In some cases, the same sink node is put into the tree multiple times in a single route.
         // So it is possible to hit the same node index multiple times during traceback. Create a
         // separate rt_node for each sink with the same node index.
+        //ESR API Access (Get node's type)
         if (itr == rr_node_to_rt.end() || device_ctx.rr_nodes[inode].type() == SINK) {
             //Create
 
@@ -813,7 +821,7 @@ static t_trace* traceback_to_route_tree_branch(t_trace* trace,
             node->R_upstream = std::numeric_limits<float>::quiet_NaN();
             node->C_downstream = std::numeric_limits<float>::quiet_NaN();
             node->Tdel = std::numeric_limits<float>::quiet_NaN();
-
+            //ESR API Access (Get node's type)
             auto node_type = device_ctx.rr_nodes[inode].type();
             if (node_type == IPIN || node_type == SINK)
                 node->re_expand = false;
@@ -954,6 +962,7 @@ t_trace* traceback_from_route_tree(ClusterNetId inet, const t_rt_node* root, int
         nodes.insert(trace->index);
 
         //Sanity check that number of sinks match expected
+        //ESR API Access (Get node's type)
         if (device_ctx.rr_nodes[trace->index].type() == SINK) {
             num_trace_sinks += 1;
         }
@@ -978,7 +987,7 @@ static t_rt_node* prune_route_tree_recurr(t_rt_node* node, CBRR& connections_inf
 
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
-
+    //ESR API Access (Get node's capacity)
     bool congested = (route_ctx.rr_node_route_inf[node->inode].occ() > device_ctx.rr_nodes[node->inode].capacity());
     int node_set = -1;
     auto itr = device_ctx.rr_node_to_non_config_node_set.find(node->inode);
@@ -1036,7 +1045,7 @@ static t_rt_node* prune_route_tree_recurr(t_rt_node* node, CBRR& connections_inf
             edge = edge->next;
         }
     }
-
+    //ESR API Access (Get node's type)
     if (device_ctx.rr_nodes[node->inode].type() == SINK) {
         if (!force_prune) {
             //Valid path to sink
@@ -1172,9 +1181,9 @@ t_rt_node* prune_route_tree(t_rt_node* rt_root, CBRR& connections_inf, std::vect
 
     auto& device_ctx = g_vpr_ctx.device();
     auto& route_ctx = g_vpr_ctx.routing();
-
+    //ESR API Access (Get node's type)
     VTR_ASSERT_MSG(device_ctx.rr_nodes[rt_root->inode].type() == SOURCE, "Root of route tree must be SOURCE");
-
+    //ESR API Access (Get node's capacity) 
     VTR_ASSERT_MSG(route_ctx.rr_node_route_inf[rt_root->inode].occ() <= device_ctx.rr_nodes[rt_root->inode].capacity(),
                    "Route tree root/SOURCE should never be congested");
 
@@ -1258,6 +1267,7 @@ static void print_node(const t_rt_node* rt_node) {
     auto& device_ctx = g_vpr_ctx.device();
 
     int inode = rt_node->inode;
+    //ESR API Access (Get node's type)
     t_rr_type node_type = device_ctx.rr_nodes[inode].type();
     VTR_LOG("%5.1e %5.1e %2d%6s|%-6d-> ", rt_node->C_downstream, rt_node->R_upstream,
             rt_node->re_expand, rr_node_typename[node_type], inode);
@@ -1278,6 +1288,7 @@ static void print_node_congestion(const t_rt_node* rt_node) {
 
     int inode = rt_node->inode;
     const auto& node_inf = route_ctx.rr_node_route_inf[inode];
+    //ESR API Access (Get node)
     const auto& node = device_ctx.rr_nodes[inode];
     VTR_LOG("%2d %2d|%-6d-> ", node_inf.acc_cost, rt_node->Tdel,
             node_inf.occ(), node.capacity(), inode);
@@ -1369,18 +1380,21 @@ bool is_valid_route_tree(const t_rt_node* root) {
     short iswitch = root->parent_switch;
     if (root->parent_node) {
         if (device_ctx.rr_switch_inf[iswitch].buffered()) {
+            //ESR API Access (Get node's Resistance)
             float R_upstream_check = device_ctx.rr_nodes[inode].R() + device_ctx.rr_switch_inf[iswitch].R;
             if (!vtr::isclose(root->R_upstream, R_upstream_check, RES_REL_TOL, RES_ABS_TOL)) {
                 VTR_LOG("%d mismatch R upstream %e supposed %e\n", inode, root->R_upstream, R_upstream_check);
                 return false;
             }
         } else {
+            //ESR API Access (Get node's Resistance)
             float R_upstream_check = device_ctx.rr_nodes[inode].R() + root->parent_node->R_upstream + device_ctx.rr_switch_inf[iswitch].R;
             if (!vtr::isclose(root->R_upstream, R_upstream_check, RES_REL_TOL, RES_ABS_TOL)) {
                 VTR_LOG("%d mismatch R upstream %e supposed %e\n", inode, root->R_upstream, R_upstream_check);
                 return false;
             }
         }
+        //ESR API Access (Get node's Resistance [two spots])
     } else if (root->R_upstream != device_ctx.rr_nodes[inode].R()) {
         VTR_LOG("%d mismatch R upstream %e supposed %e\n", inode, root->R_upstream, device_ctx.rr_nodes[inode].R());
         return false;
@@ -1392,6 +1406,7 @@ bool is_valid_route_tree(const t_rt_node* root) {
     // sink, must not be congested
     if (!edge) {
         int occ = route_ctx.rr_node_route_inf[inode].occ();
+        //ESR API Access (Get node's capacity)
         int capacity = device_ctx.rr_nodes[inode].capacity();
         if (occ > capacity) {
             VTR_LOG("SINK %d occ %d > cap %d\n", inode, occ, capacity);
@@ -1423,7 +1438,7 @@ bool is_valid_route_tree(const t_rt_node* root) {
         }
         edge = edge->next;
     }
-
+    //ESR API Access (Get node's Capacitance)
     float C_downstream_check = C_downstream_children + device_ctx.rr_nodes[inode].C();
     if (!vtr::isclose(root->C_downstream, C_downstream_check, CAP_REL_TOL, CAP_ABS_TOL)) {
         VTR_LOG("%d mismatch C downstream %e supposed %e\n", inode, root->C_downstream, C_downstream_check);
@@ -1439,6 +1454,7 @@ bool is_uncongested_route_tree(const t_rt_node* root) {
     auto& device_ctx = g_vpr_ctx.device();
 
     int inode = root->inode;
+    //ESR API Access (Get node's capacity)
     if (route_ctx.rr_node_route_inf[inode].occ() > device_ctx.rr_nodes[inode].capacity()) {
         //This node is congested
         return false;
@@ -1471,6 +1487,7 @@ init_route_tree_to_source_no_net(int inode) {
     rt_root->re_expand = true;
     rt_root->inode = inode;
     rt_root->net_pin_index = OPEN;
+    //ESR API Access (Get node's Capacitance and Resistance [4 times])
     rt_root->C_downstream = device_ctx.rr_nodes[inode].C();
     rt_root->R_upstream = device_ctx.rr_nodes[inode].R();
     rt_root->Tdel = 0.5 * device_ctx.rr_nodes[inode].R() * device_ctx.rr_nodes[inode].C();

vpr/src/route/route_tree_timing.cpp

@@ -16,7 +16,7 @@ vtr::Matrix<float> calculate_routing_usage(t_rr_type rr_type) {
         t_trace* tptr = route_ctx.trace[net].head;
         while (tptr != nullptr) {
             int inode = tptr->index;
-
+            
             if (device_ctx.rr_nodes[inode].type() == rr_type) {
                 rr_nodes.insert(inode);
             }

vpr/src/route/route_util.cpp

@@ -26,7 +26,7 @@
 /* This function is used to write the rr_graph into xml format into a a file with name: file_name */
 void write_rr_graph(const char* file_name) {
     auto& device_ctx = g_vpr_ctx.mutable_device();
-    VTR_LOG("Just making sure i can add this...\n");
+    VTR_LOG("#ESR write_rr_graph\n");
     RrGraphSerializer reader(
         /*graph_type=*/t_graph_type(),
         /*base_cost_type=*/e_base_cost_type(),