Skip to content

Commit ecd1aef

Browse files
amin1377amin1377
committed
Solve warnings - make format
1 parent 6dc9544 commit ecd1aef

File tree

6 files changed

+8
-54
lines changed

6 files changed

+8
-54
lines changed

‎libs/libarchfpga/src/physical_types_util.cpp

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -858,7 +858,7 @@ t_logical_block_type_ptr get_logical_block_from_class_physical_num(t_physical_ti
858858
}
859859

860860
std::vector<int> get_pin_list_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
861-
if(is_class_on_tile(physical_tile, class_physical_num)) {
861+
if (is_class_on_tile(physical_tile, class_physical_num)) {
862862
const t_class& pin_class = physical_tile->class_inf[class_physical_num];
863863
return pin_class.pinlist;
864864
} else {
@@ -868,7 +868,7 @@ std::vector<int> get_pin_list_from_class_physical_num(t_physical_tile_type_ptr p
868868
}
869869

870870
PortEquivalence get_port_equivalency_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
871-
if(is_class_on_tile(physical_tile, class_physical_num)) {
871+
if (is_class_on_tile(physical_tile, class_physical_num)) {
872872
const t_class& pin_class = physical_tile->class_inf[class_physical_num];
873873
return pin_class.equivalence;
874874
} else {
@@ -878,27 +878,23 @@ PortEquivalence get_port_equivalency_from_class_physical_num(t_physical_tile_typ
878878
}
879879

880880
e_pin_type get_class_type_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
881-
882881
if (is_class_on_tile(physical_tile, class_physical_num)) {
883882
return physical_tile->class_inf[class_physical_num].type;
884883

885884
} else {
886885
const t_class& pin_class = physical_tile->internal_class_inf.at(class_physical_num);
887886
return pin_class.type;
888887
}
889-
890888
}
891889

892890
int get_class_num_pins_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
893-
894891
if (is_class_on_tile(physical_tile, class_physical_num)) {
895892
return physical_tile->class_inf[class_physical_num].num_pins;
896893

897894
} else {
898895
const t_class& pin_class = physical_tile->internal_class_inf.at(class_physical_num);
899896
return pin_class.num_pins;
900897
}
901-
902898
}
903899

904900
int get_pin_physical_num_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num, int pin_logical_num) {
@@ -1039,7 +1035,7 @@ const t_pb_graph_pin* get_pb_pin_from_pin_physical_num(t_physical_tile_type_ptr
10391035
}
10401036

10411037
PortEquivalence get_port_equivalency_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int pin_physical_num) {
1042-
if(is_pin_on_tile(physical_tile, pin_physical_num)) {
1038+
if (is_pin_on_tile(physical_tile, pin_physical_num)) {
10431039
const t_class& pin_class = physical_tile->class_inf[physical_tile->pin_class[pin_physical_num]];
10441040
return pin_class.equivalence;
10451041
} else {

‎vpr/src/base/ShowSetup.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@ static void ShowRouterOpts(const t_router_opts& RouterOpts) {
244244
}
245245

246246
VTR_LOG("RouterOpts.flat_routing: ");
247-
if(RouterOpts.flat_routing) {
247+
if (RouterOpts.flat_routing) {
248248
VTR_LOG("true\n");
249249
} else {
250250
VTR_LOG("false\n");

‎vpr/src/draw/draw_searchbar.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ ezgl::rectangle draw_get_rr_chan_bbox(int inode) {
105105

106106
void draw_highlight_blocks_color(t_logical_block_type_ptr type,
107107
ClusterBlockId blk_id) {
108-
int k, iclass;
108+
int k;
109109
ClusterBlockId fanblk;
110110

111111
t_draw_state* draw_state = get_draw_state_vars();

‎vpr/src/pack/pb_type_graph.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ void alloc_and_load_all_pb_graphs(bool load_power_structures, bool is_flat) {
148148
type.pb_type, 0, load_power_structures, pin_count_in_cluster);
149149
type.pb_graph_head->total_pb_pins = pin_count_in_cluster;
150150
load_pin_classes_in_pb_graph_head(type.pb_graph_head);
151-
if(is_flat) {
151+
if (is_flat) {
152152
set_pins_logical_num(&type);
153153
add_logical_classes(&type);
154154
}
@@ -467,7 +467,6 @@ static std::vector<const t_pb_graph_node*> get_all_logical_block_pb_graph_nodes(
467467
}
468468

469469
static void add_logical_classes(t_logical_block_type* logical_block) {
470-
471470
auto pb_graph_nodes = get_all_logical_block_pb_graph_nodes(logical_block);
472471
for (auto pb_graph_node : pb_graph_nodes) {
473472
/* There are three types of ports which can be defined for each block : Input - Output - Clock

‎vpr/src/place/timing_place_lookup.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -105,7 +105,7 @@ static void generic_compute_matrix_iterative_astar(
105105
const t_router_opts& router_opts,
106106
bool measure_directconnect,
107107
const std::set<std::string>& allowed_types,
108-
bool is_flat);
108+
bool /***/);
109109

110110
static void generic_compute_matrix_dijkstra_expansion(
111111
RouterDelayProfiler& route_profiler,
@@ -563,7 +563,7 @@ static void generic_compute_matrix_iterative_astar(
563563
const t_router_opts& router_opts,
564564
bool measure_directconnect,
565565
const std::set<std::string>& allowed_types,
566-
bool is_flat) {
566+
bool /***/) {
567567
//vtr::ScopedStartFinishTimer t(vtr::string_fmt("Profiling from (%d,%d)", source_x, source_y));
568568

569569
int delta_x, delta_y;

‎vpr/src/route/rr_graph.cpp

Lines changed: 0 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -306,13 +306,6 @@ static RRNodeId get_pin_rr_node_id(RRGraphBuilder& rr_graph_builder,
306306
const int j,
307307
int pin_physical_num);
308308

309-
static t_pin_spec get_pin_spec_from_class(RRGraphBuilder& rr_graph_builder,
310-
t_physical_tile_type_ptr physical_tile,
311-
int i,
312-
int j,
313-
int pin_logical_num,
314-
int class_id);
315-
316309
static void build_rr_chan(RRGraphBuilder& rr_graph_builder,
317310
const int i,
318311
const int j,
@@ -1713,7 +1706,6 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
17131706
auto type = grid[i][j].type;
17141707
int num_class = (int)type->class_inf.size();
17151708
int num_pins = type->num_pins;
1716-
const std::vector<int>& pin_class = type->pin_class;
17171709

17181710
auto& device_ctx = g_vpr_ctx.device();
17191711
auto& mutable_device_ctx = g_vpr_ctx.mutable_device();
@@ -2132,39 +2124,6 @@ static RRNodeId get_pin_rr_node_id(RRGraphBuilder& rr_graph_builder,
21322124
return RRNodeId::INVALID();
21332125
}
21342126

2135-
static t_pin_spec get_pin_spec_from_class(RRGraphBuilder& rr_graph_builder,
2136-
t_physical_tile_type_ptr physical_tile,
2137-
int i,
2138-
int j,
2139-
int pin_logical_num,
2140-
int class_id) {
2141-
t_pin_spec pin_spec;
2142-
t_rr_type node_type = NUM_RR_TYPES;
2143-
int pin_ptc;
2144-
RRNodeId node_id = RRNodeId::INVALID();
2145-
pin_ptc = get_pin_physical_num_from_class_physical_num(physical_tile, class_id, pin_logical_num);
2146-
VTR_ASSERT(pin_ptc != -1);
2147-
2148-
// get node type
2149-
auto pin_type = get_pin_type_from_pin_physical_num(physical_tile, pin_ptc);
2150-
VTR_ASSERT(pin_type == DRIVER || pin_type == RECEIVER);
2151-
node_type = (pin_type == e_pin_type::DRIVER) ? t_rr_type::OPIN : t_rr_type::IPIN;
2152-
2153-
// get node id
2154-
node_id = get_pin_rr_node_id(rr_graph_builder,
2155-
physical_tile,
2156-
i,
2157-
j,
2158-
pin_ptc);
2159-
2160-
VTR_ASSERT(node_id != RRNodeId::INVALID());
2161-
2162-
pin_spec.pin_type = node_type;
2163-
pin_spec.pin_rr_node_id = node_id;
2164-
pin_spec.pin_ptc = pin_ptc;
2165-
return pin_spec;
2166-
}
2167-
21682127
/* Allocates/loads edges for nodes belonging to specified channel segment and initializes
21692128
* node properties such as cost, occupancy and capacity */
21702129
static void build_rr_chan(RRGraphBuilder& rr_graph_builder,

0 commit comments

Comments
 (0)