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amin1377amin1377
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Change some of the direct access to physical tile class_inf to use helper functions
1 parent 39aeb4a commit 6dc9544

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6 files changed

+71
-43
lines changed

6 files changed

+71
-43
lines changed

‎libs/libarchfpga/src/physical_types_util.cpp

Lines changed: 38 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -857,39 +857,48 @@ t_logical_block_type_ptr get_logical_block_from_class_physical_num(t_physical_ti
857857
return nullptr;
858858
}
859859

860-
e_pin_type get_class_type_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num) {
861-
e_pin_type class_type;
860+
std::vector<int> get_pin_list_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
861+
if(is_class_on_tile(physical_tile, class_physical_num)) {
862+
const t_class& pin_class = physical_tile->class_inf[class_physical_num];
863+
return pin_class.pinlist;
864+
} else {
865+
const t_class& pin_class = physical_tile->internal_class_inf.at(class_physical_num);
866+
return pin_class.pinlist;
867+
}
868+
}
862869

863-
bool is_on_tile = is_class_on_tile(physical_tile, physical_class_num);
870+
PortEquivalence get_port_equivalency_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
871+
if(is_class_on_tile(physical_tile, class_physical_num)) {
872+
const t_class& pin_class = physical_tile->class_inf[class_physical_num];
873+
return pin_class.equivalence;
874+
} else {
875+
const t_class& pin_class = physical_tile->internal_class_inf.at(class_physical_num);
876+
return pin_class.equivalence;
877+
}
878+
}
864879

865-
if (!is_on_tile) {
866-
auto logical_block = get_logical_block_from_class_physical_num(physical_tile, physical_class_num);
867-
int class_logical_num = get_class_logical_num_from_class_physical_num(physical_tile, physical_class_num);
868-
class_type = logical_block->logical_class_inf[class_logical_num].type;
880+
e_pin_type get_class_type_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
881+
882+
if (is_class_on_tile(physical_tile, class_physical_num)) {
883+
return physical_tile->class_inf[class_physical_num].type;
869884

870885
} else {
871-
VTR_ASSERT(is_on_tile == true);
872-
class_type = physical_tile->class_inf[physical_class_num].type;
886+
const t_class& pin_class = physical_tile->internal_class_inf.at(class_physical_num);
887+
return pin_class.type;
873888
}
874889

875-
return class_type;
876890
}
877891

878-
int get_class_num_pins_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num) {
879-
int num_pins = -1;
880-
bool is_on_tile = is_class_on_tile(physical_tile, physical_class_num);
892+
int get_class_num_pins_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num) {
881893

882-
if (!is_on_tile) {
883-
auto logical_block = get_logical_block_from_class_physical_num(physical_tile, physical_class_num);
884-
int class_logical_num = get_class_logical_num_from_class_physical_num(physical_tile, physical_class_num);
885-
num_pins = logical_block->logical_class_inf[class_logical_num].num_pins;
894+
if (is_class_on_tile(physical_tile, class_physical_num)) {
895+
return physical_tile->class_inf[class_physical_num].num_pins;
886896

887897
} else {
888-
VTR_ASSERT(is_on_tile == true);
889-
num_pins = physical_tile->class_inf[physical_class_num].num_pins;
898+
const t_class& pin_class = physical_tile->internal_class_inf.at(class_physical_num);
899+
return pin_class.num_pins;
890900
}
891901

892-
return num_pins;
893902
}
894903

895904
int get_pin_physical_num_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num, int pin_logical_num) {
@@ -1029,6 +1038,15 @@ const t_pb_graph_pin* get_pb_pin_from_pin_physical_num(t_physical_tile_type_ptr
10291038
return logical_block->pin_logical_num_to_pb_pin_mapping.at(logical_num);
10301039
}
10311040

1041+
PortEquivalence get_port_equivalency_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int pin_physical_num) {
1042+
if(is_pin_on_tile(physical_tile, pin_physical_num)) {
1043+
const t_class& pin_class = physical_tile->class_inf[physical_tile->pin_class[pin_physical_num]];
1044+
return pin_class.equivalence;
1045+
} else {
1046+
const t_class& pin_class = physical_tile->internal_class_inf.at(physical_tile->internal_pin_class.at(pin_physical_num));
1047+
return pin_class.equivalence;
1048+
}
1049+
}
10321050
e_pin_type get_pin_type_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int pin_physical_num) {
10331051
if (is_pin_on_tile(physical_tile, pin_physical_num)) {
10341052
const t_class& pin_class = physical_tile->class_inf[physical_tile->pin_class[pin_physical_num]];

‎libs/libarchfpga/src/physical_types_util.h

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -311,9 +311,13 @@ std::tuple<const t_sub_tile*, int> get_sub_tile_from_class_physical_num(t_physic
311311

312312
t_logical_block_type_ptr get_logical_block_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num);
313313

314-
e_pin_type get_class_type_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num);
314+
std::vector<int> get_pin_list_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
315315

316-
int get_class_num_pins_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num);
316+
PortEquivalence get_port_equivalency_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
317+
318+
e_pin_type get_class_type_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
319+
320+
int get_class_num_pins_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int class_physical_num);
317321

318322
int get_pin_physical_num_from_class_physical_num(t_physical_tile_type_ptr physical_tile, int physical_class_num, int pin_logical_num);
319323

@@ -344,6 +348,8 @@ t_logical_block_type_ptr get_logical_block_from_pin_physical_num(t_physical_tile
344348

345349
const t_pb_graph_pin* get_pb_pin_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num);
346350

351+
PortEquivalence get_port_equivalency_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int pin_physical_num);
352+
347353
e_pin_type get_pin_type_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num);
348354

349355
int get_class_num_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int pin_physical_num);

‎libs/libarchfpga/src/read_xml_arch_file.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -534,12 +534,12 @@ static void LoadPinLoc(pugi::xml_node Locations,
534534
std::vector<int> input_pins;
535535
std::vector<int> output_pins;
536536
for (int pin_num = 0; pin_num < type->num_pins; ++pin_num) {
537-
int iclass = type->pin_class[pin_num];
537+
auto class_type = get_pin_type_from_pin_physical_num(type, pin_num);
538538

539-
if (type->class_inf[iclass].type == RECEIVER) {
539+
if (class_type == RECEIVER) {
540540
input_pins.push_back(pin_num);
541541
} else {
542-
VTR_ASSERT(type->class_inf[iclass].type == DRIVER);
542+
VTR_ASSERT(class_type == DRIVER);
543543
output_pins.push_back(pin_num);
544544
}
545545
}

‎vpr/src/draw/draw_searchbar.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -120,9 +120,9 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type,
120120
auto physical_tile = physical_tile_type(blk_id);
121121
int physical_pin = get_physical_pin(physical_tile, type, k);
122122

123-
iclass = physical_tile->pin_class[physical_pin];
123+
auto class_type = get_pin_type_from_pin_physical_num(physical_tile, physical_pin);
124124

125-
if (physical_tile->class_inf[iclass].type == DRIVER) { /* Fanout */
125+
if (class_type == DRIVER) { /* Fanout */
126126
if (draw_state->block_color(blk_id) == SELECTED_COLOR) {
127127
/* If block already highlighted, de-highlight the fanout. (the deselect case)*/
128128
draw_state->net_color[net_id] = ezgl::BLACK;

‎vpr/src/route/route_common.cpp

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -872,13 +872,13 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() {
872872

873873
if (!net || (net && cluster_ctx.clb_nlist.net_sinks(net).size() == 0)) {
874874
//There is no external net connected to this pin
875-
875+
auto port_eq = get_port_equivalency_from_pin_physical_num(type, clb_pin);
876876
iclass = type->pin_class[clb_pin];
877877

878-
if (type->class_inf[iclass].equivalence == PortEquivalence::INSTANCE) {
878+
if (port_eq == PortEquivalence::INSTANCE) {
879879
//The pin is part of an instance equivalent class, hence we need to reserve a pin
880880

881-
VTR_ASSERT(type->class_inf[iclass].type == DRIVER);
881+
VTR_ASSERT(get_pin_type_from_pin_physical_num(type, clb_pin) == DRIVER);
882882

883883
/* Check to make sure class is in same range as that assigned to block */
884884
VTR_ASSERT(iclass >= class_range.low && iclass <= class_range.high);
@@ -1047,7 +1047,8 @@ static vtr::vector<ClusterBlockId, std::vector<int>> load_rr_clb_sources(const R
10471047
i = place_ctx.block_locs[blk_id].loc.x;
10481048
j = place_ctx.block_locs[blk_id].loc.y;
10491049

1050-
if (type->class_inf[iclass].type == DRIVER)
1050+
auto class_type = get_class_type_from_class_physical_num(type, iclass);
1051+
if (class_type == DRIVER)
10511052
rr_type = SOURCE;
10521053
else
10531054
rr_type = SINK;
@@ -1401,7 +1402,8 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f
14011402
num_local_opin = route_ctx.clb_opins_used_locally[blk_id][iclass].size();
14021403

14031404
if (num_local_opin == 0) continue;
1404-
VTR_ASSERT(type->class_inf[iclass].equivalence == PortEquivalence::INSTANCE);
1405+
auto port_eq = get_port_equivalency_from_class_physical_num(type, iclass);
1406+
VTR_ASSERT(port_eq == PortEquivalence::INSTANCE);
14051407

14061408
/* Always 0 for pads and for RECEIVER (IPIN) classes */
14071409
for (ipin = 0; ipin < num_local_opin; ipin++) {
@@ -1423,7 +1425,8 @@ void reserve_locally_used_opins(HeapInterface* heap, float pres_fac, float acc_f
14231425

14241426
if (num_local_opin == 0) continue;
14251427

1426-
VTR_ASSERT(type->class_inf[iclass].equivalence == PortEquivalence::INSTANCE);
1428+
auto class_eq = get_port_equivalency_from_class_physical_num(type, iclass);
1429+
VTR_ASSERT(class_eq == PortEquivalence::INSTANCE);
14271430

14281431
//From the SRC node we walk through it's out going edges to collect the
14291432
//OPIN nodes. We then push them onto a heap so the OPINs with lower

‎vpr/src/route/rr_graph.cpp

Lines changed: 11 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1712,7 +1712,6 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
17121712

17131713
auto type = grid[i][j].type;
17141714
int num_class = (int)type->class_inf.size();
1715-
const std::vector<t_class>& class_inf = type->class_inf;
17161715
int num_pins = type->num_pins;
17171716
const std::vector<int>& pin_class = type->pin_class;
17181717

@@ -1724,7 +1723,8 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
17241723
//int edges_created =0;
17251724
for (int iclass = 0; iclass < num_class; ++iclass) {
17261725
RRNodeId inode = RRNodeId::INVALID();
1727-
if (class_inf[iclass].type == DRIVER) { /* SOURCE */
1726+
auto class_type = get_class_type_from_class_physical_num(type, iclass);
1727+
if (class_type == DRIVER) { /* SOURCE */
17281728
inode = rr_graph_builder.node_lookup().find_node(i, j, SOURCE, iclass);
17291729
VTR_ASSERT(inode);
17301730

@@ -1733,8 +1733,8 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
17331733
std::vector<RRNodeId> opin_nodes;
17341734
for (int width_offset = 0; width_offset < type->width; ++width_offset) {
17351735
for (int height_offset = 0; height_offset < type->height; ++height_offset) {
1736-
for (int ipin = 0; ipin < class_inf[iclass].num_pins; ++ipin) {
1737-
int pin_num = class_inf[iclass].pinlist[ipin];
1736+
auto pin_list = get_pin_list_from_class_physical_num(type, iclass);
1737+
for (int pin_num : pin_list) {
17381738
std::vector<RRNodeId> physical_pins = rr_graph_builder.node_lookup().find_nodes_at_all_sides(i + width_offset, j + height_offset, OPIN, pin_num);
17391739
opin_nodes.insert(opin_nodes.end(), physical_pins.begin(), physical_pins.end());
17401740
}
@@ -1750,7 +1750,7 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
17501750
rr_graph_builder.set_node_cost_index(inode, RRIndexedDataId(SOURCE_COST_INDEX));
17511751
rr_graph_builder.set_node_type(inode, SOURCE);
17521752
} else { /* SINK */
1753-
VTR_ASSERT(class_inf[iclass].type == RECEIVER);
1753+
VTR_ASSERT(class_type == RECEIVER);
17541754
inode = rr_graph_builder.node_lookup().find_node(i, j, SINK, iclass);
17551755

17561756
VTR_ASSERT(inode);
@@ -1770,7 +1770,7 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
17701770
}
17711771

17721772
/* Things common to both SOURCEs and SINKs. */
1773-
rr_graph_builder.set_node_capacity(inode, class_inf[iclass].num_pins);
1773+
rr_graph_builder.set_node_capacity(inode, get_class_num_pins_from_class_physical_num(type, iclass));
17741774
rr_graph_builder.set_node_coordinates(inode, i, j, i + type->width - 1, j + type->height - 1);
17751775
float R = 0.;
17761776
float C = 0.;
@@ -1787,15 +1787,16 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
17871787
for (int height_offset = 0; height_offset < type->height; ++height_offset) {
17881788
if (type->pinloc[width_offset][height_offset][side][ipin]) {
17891789
RRNodeId inode = RRNodeId::INVALID();
1790-
int iclass = pin_class[ipin];
1790+
auto pin_type = get_pin_type_from_pin_physical_num(type, ipin);
1791+
auto class_physical_num = get_class_num_from_pin_physical_num(type, ipin);
17911792

1792-
if (class_inf[iclass].type == RECEIVER) {
1793+
if (pin_type == RECEIVER) {
17931794
//Connect the input pin to the sink
17941795
inode = rr_graph_builder.node_lookup().find_node(i + width_offset, j + height_offset, IPIN, ipin, side);
17951796

17961797
/* Input pins are uniquified, we may not always find one */
17971798
if (inode) {
1798-
RRNodeId to_node = rr_graph_builder.node_lookup().find_node(i, j, SINK, iclass);
1799+
RRNodeId to_node = rr_graph_builder.node_lookup().find_node(i, j, SINK, class_physical_num);
17991800

18001801
//Add info about the edge to be created
18011802
rr_edges_to_create.emplace_back(inode, to_node, delayless_switch);
@@ -1804,7 +1805,7 @@ static void build_rr_sinks_sources(RRGraphBuilder& rr_graph_builder,
18041805
rr_graph_builder.set_node_type(inode, IPIN);
18051806
}
18061807
} else {
1807-
VTR_ASSERT(class_inf[iclass].type == DRIVER);
1808+
VTR_ASSERT(pin_type == DRIVER);
18081809
//Initialize the output pin
18091810
// Note that we leave it's out-going edges unconnected (they will be hooked up to global routing later)
18101811
inode = rr_graph_builder.node_lookup().find_node(i + width_offset, j + height_offset, OPIN, ipin, side);

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