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Odin: regenerate expected results
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9 files changed

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-51
lines changed

9 files changed

+535
-51
lines changed

‎ODIN_II/regression_test/benchmark/suite/light_suite/task_list.conf

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@@ -1,5 +1,6 @@
11
rtl_reg
22
regression_test/benchmark/task/arch_sweep
3+
regression_test/benchmark/task/fpu/*
34
regression_test/benchmark/task/cmd_line_args/*
45
regression_test/benchmark/task/preprocessor
56
regression_test/benchmark/task/operators

‎ODIN_II/regression_test/benchmark/task/fpu/hard_logic/simulation_result.json

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{
2+
"hard_logic/bfly/hard_fpu_arch_timing": {
3+
"test_name": "hard_logic/bfly/hard_fpu_arch_timing",
4+
"architecture": "hard_fpu_arch_timing.xml",
5+
"blif": "bfly.blif",
6+
"exit": 134,
7+
"errors": [
8+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
9+
]
10+
},
11+
"hard_logic/bgm/hard_fpu_arch_timing": {
12+
"test_name": "hard_logic/bgm/hard_fpu_arch_timing",
13+
"architecture": "hard_fpu_arch_timing.xml",
14+
"blif": "bgm.blif",
15+
"exit": 134,
16+
"errors": [
17+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
18+
]
19+
},
20+
"hard_logic/dscg/hard_fpu_arch_timing": {
21+
"test_name": "hard_logic/dscg/hard_fpu_arch_timing",
22+
"architecture": "hard_fpu_arch_timing.xml",
23+
"blif": "dscg.blif",
24+
"exit": 134,
25+
"errors": [
26+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_add~0 to a valid type."
27+
]
28+
},
29+
"hard_logic/fir/hard_fpu_arch_timing": {
30+
"test_name": "hard_logic/fir/hard_fpu_arch_timing",
31+
"architecture": "hard_fpu_arch_timing.xml",
32+
"blif": "fir.blif",
33+
"exit": 134,
34+
"errors": [
35+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
36+
]
37+
},
38+
"hard_logic/mm3/hard_fpu_arch_timing": {
39+
"test_name": "hard_logic/mm3/hard_fpu_arch_timing",
40+
"architecture": "hard_fpu_arch_timing.xml",
41+
"blif": "mm3.blif",
42+
"exit": 134,
43+
"errors": [
44+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
45+
]
46+
},
47+
"hard_logic/ode/hard_fpu_arch_timing": {
48+
"test_name": "hard_logic/ode/hard_fpu_arch_timing",
49+
"architecture": "hard_fpu_arch_timing.xml",
50+
"blif": "ode.blif",
51+
"exit": 134,
52+
"errors": [
53+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~0 to a valid type."
54+
]
55+
},
56+
"hard_logic/syn2/hard_fpu_arch_timing": {
57+
"test_name": "hard_logic/syn2/hard_fpu_arch_timing",
58+
"architecture": "hard_fpu_arch_timing.xml",
59+
"blif": "syn2.blif",
60+
"exit": 134,
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"errors": [
62+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_mul~5 to a valid type."
63+
]
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},
65+
"hard_logic/syn7/hard_fpu_arch_timing": {
66+
"test_name": "hard_logic/syn7/hard_fpu_arch_timing",
67+
"architecture": "hard_fpu_arch_timing.xml",
68+
"blif": "syn7.blif",
69+
"exit": 134,
70+
"errors": [
71+
"[OUTPUT_BLIF] Could not resolve memory hard block fpu_add~0 to a valid type."
72+
]
73+
},
74+
"DEFAULT": {
75+
"test_name": "n/a",
76+
"architecture": "n/a",
77+
"blif": "n/a",
78+
"exit": 0,
79+
"leaks": 0,
80+
"errors": [],
81+
"warnings": [],
82+
"expectation": [],
83+
"max_rss(MiB)": -1,
84+
"exec_time(ms)": -1,
85+
"simulation_time(ms)": -1,
86+
"test_coverage(%)": -1,
87+
"Latch Drivers": 0,
88+
"Pi": 0,
89+
"Po": 0,
90+
"logic element": 0,
91+
"latch": 0,
92+
"Adder": -1,
93+
"Multiplier": -1,
94+
"Memory": -1,
95+
"Hard Ip": -1,
96+
"generic logic size": -1,
97+
"Longest Path": 0,
98+
"Average Path": 0,
99+
"Estimated LUTs": 0,
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"Total Node": 0
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}
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}

‎ODIN_II/regression_test/benchmark/task/fpu/hard_logic/synthesis_result.json

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{
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"hard_logic/bfly/hard_fpu_arch_timing": {
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"test_name": "hard_logic/bfly/hard_fpu_arch_timing",
4+
"architecture": "hard_fpu_arch_timing.xml",
5+
"verilog": "bfly.v",
6+
"max_rss(MiB)": 68.7,
7+
"exec_time(ms)": 90.4,
8+
"synthesis_time(ms)": 28.7,
9+
"Latch Drivers": 1,
10+
"Pi": 192,
11+
"Po": 64,
12+
"latch": 384,
13+
"Hard Ip": 8,
14+
"generic logic size": 4,
15+
"Longest Path": 9,
16+
"Average Path": 5,
17+
"Total Node": 393
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},
19+
"hard_logic/bgm/hard_fpu_arch_timing": {
20+
"test_name": "hard_logic/bgm/hard_fpu_arch_timing",
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"architecture": "hard_fpu_arch_timing.xml",
22+
"verilog": "bgm.v",
23+
"max_rss(MiB)": 81.3,
24+
"exec_time(ms)": 152.5,
25+
"synthesis_time(ms)": 90.8,
26+
"Latch Drivers": 1,
27+
"Pi": 256,
28+
"Po": 32,
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"latch": 384,
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"Hard Ip": 20,
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"generic logic size": 4,
32+
"Longest Path": 11,
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"Average Path": 5,
34+
"Total Node": 405
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},
36+
"hard_logic/dscg/hard_fpu_arch_timing": {
37+
"test_name": "hard_logic/dscg/hard_fpu_arch_timing",
38+
"architecture": "hard_fpu_arch_timing.xml",
39+
"verilog": "dscg.v",
40+
"max_rss(MiB)": 67.2,
41+
"exec_time(ms)": 158.4,
42+
"synthesis_time(ms)": 48,
43+
"Latch Drivers": 1,
44+
"Pi": 128,
45+
"Po": 64,
46+
"latch": 384,
47+
"Hard Ip": 8,
48+
"generic logic size": 4,
49+
"Longest Path": 10,
50+
"Average Path": 5,
51+
"Total Node": 393
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},
53+
"hard_logic/fir/hard_fpu_arch_timing": {
54+
"test_name": "hard_logic/fir/hard_fpu_arch_timing",
55+
"architecture": "hard_fpu_arch_timing.xml",
56+
"verilog": "fir.v",
57+
"max_rss(MiB)": 72.1,
58+
"exec_time(ms)": 170.5,
59+
"synthesis_time(ms)": 59.8,
60+
"Latch Drivers": 1,
61+
"Pi": 160,
62+
"Po": 32,
63+
"latch": 608,
64+
"Hard Ip": 7,
65+
"generic logic size": 4,
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"Longest Path": 23,
67+
"Average Path": 5,
68+
"Total Node": 616
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},
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"hard_logic/mm3/hard_fpu_arch_timing": {
71+
"test_name": "hard_logic/mm3/hard_fpu_arch_timing",
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"architecture": "hard_fpu_arch_timing.xml",
73+
"verilog": "mm3.v",
74+
"max_rss(MiB)": 63.2,
75+
"exec_time(ms)": 78.3,
76+
"synthesis_time(ms)": 16.4,
77+
"Latch Drivers": 1,
78+
"Pi": 192,
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"Po": 32,
80+
"latch": 192,
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"Hard Ip": 5,
82+
"generic logic size": 4,
83+
"Longest Path": 10,
84+
"Average Path": 5,
85+
"Total Node": 198
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},
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"hard_logic/ode/hard_fpu_arch_timing": {
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"test_name": "hard_logic/ode/hard_fpu_arch_timing",
89+
"architecture": "hard_fpu_arch_timing.xml",
90+
"verilog": "ode.v",
91+
"max_rss(MiB)": 78.1,
92+
"exec_time(ms)": 178.4,
93+
"synthesis_time(ms)": 68.2,
94+
"Latch Drivers": 1,
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"Pi": 129,
96+
"Po": 72,
97+
"logic element": 66,
98+
"latch": 800,
99+
"Hard Ip": 5,
100+
"generic logic size": 4,
101+
"Longest Path": 18,
102+
"Average Path": 3,
103+
"Estimated LUTs": 66,
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"Total Node": 872
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},
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"hard_logic/syn2/hard_fpu_arch_timing": {
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"test_name": "hard_logic/syn2/hard_fpu_arch_timing",
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"architecture": "hard_fpu_arch_timing.xml",
109+
"verilog": "syn2.v",
110+
"max_rss(MiB)": 66.2,
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"exec_time(ms)": 157.4,
112+
"synthesis_time(ms)": 47.1,
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"Latch Drivers": 1,
114+
"Pi": 160,
115+
"Po": 128,
116+
"latch": 192,
117+
"Hard Ip": 9,
118+
"generic logic size": 4,
119+
"Longest Path": 11,
120+
"Average Path": 4,
121+
"Total Node": 202
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},
123+
"hard_logic/syn7/hard_fpu_arch_timing": {
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"test_name": "hard_logic/syn7/hard_fpu_arch_timing",
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"architecture": "hard_fpu_arch_timing.xml",
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"verilog": "syn7.v",
127+
"max_rss(MiB)": 83.8,
128+
"exec_time(ms)": 158.8,
129+
"synthesis_time(ms)": 98.4,
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"Latch Drivers": 1,
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"Pi": 160,
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"Po": 128,
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"latch": 160,
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"Hard Ip": 50,
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"generic logic size": 4,
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"Longest Path": 15,
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"Average Path": 13,
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"Total Node": 211
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},
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"DEFAULT": {
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"test_name": "n/a",
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"architecture": "n/a",
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"verilog": "n/a",
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"exit": 0,
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"leaks": 0,
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"errors": [],
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"warnings": [],
148+
"expectation": [],
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"max_rss(MiB)": -1,
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"exec_time(ms)": -1,
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"synthesis_time(ms)": -1,
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"Latch Drivers": 0,
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"Pi": 0,
154+
"Po": 0,
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"logic element": 0,
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"latch": 0,
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"Adder": -1,
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"Multiplier": -1,
159+
"Memory": -1,
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"Hard Ip": -1,
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"generic logic size": -1,
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"Longest Path": 0,
163+
"Average Path": 0,
164+
"Estimated LUTs": 0,
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"Total Node": 0
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}
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}

‎ODIN_II/regression_test/benchmark/task/fpu/soft_logic/task.conf

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This file was deleted.

‎ODIN_II/regression_test/benchmark/task/keywords/defparam/simulation_result.json

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"Estimated LUTs": 12,
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"Total Node": 12
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},
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"defparam/defparam_depth_2/no_arch": {
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"test_name": "defparam/defparam_depth_2/no_arch",
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"blif": "defparam_depth_2.blif",
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"exit": 134,
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"errors": [
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"[OUTPUT_BLIF] Vector files differ."
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],
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"warnings": [
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"[OUTPUT_BLIF] Vector 0 mismatch:",
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"[OUTPUT_BLIF] Vector 1 mismatch:",
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"[OUTPUT_BLIF] Vector 2 mismatch:",
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"[OUTPUT_BLIF] Vector 3 mismatch:",
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"[OUTPUT_BLIF] Vector 4 mismatch:",
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"[OUTPUT_BLIF] Vector 5 mismatch:",
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"[OUTPUT_BLIF] Vector 6 mismatch:",
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"[OUTPUT_BLIF] Vector 7 mismatch:",
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"[OUTPUT_BLIF] Vector 8 mismatch:",
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"[OUTPUT_BLIF] Vector 9 mismatch:",
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"[OUTPUT_BLIF] Vector 10 mismatch:",
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"[OUTPUT_BLIF] Vector 11 mismatch:",
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"[OUTPUT_BLIF] Vector 12 mismatch:",
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"[OUTPUT_BLIF] Vector 13 mismatch:",
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"[OUTPUT_BLIF] Vector 14 mismatch:",
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"[OUTPUT_BLIF] Vector 15 mismatch:",
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"[OUTPUT_BLIF] Vector 16 mismatch:",
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"[OUTPUT_BLIF] Vector 17 mismatch:",
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"[OUTPUT_BLIF] Vector 18 mismatch:",
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"[OUTPUT_BLIF] Vector 19 mismatch:",
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"[OUTPUT_BLIF] Vector 20 mismatch:",
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"[OUTPUT_BLIF] Vector 21 mismatch:",
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"[OUTPUT_BLIF] Vector 22 mismatch:",
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"[OUTPUT_BLIF] Vector 23 mismatch:",
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"[OUTPUT_BLIF] Vector 24 mismatch:",
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"[OUTPUT_BLIF] Vector 25 mismatch:",
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"[OUTPUT_BLIF] Vector 26 mismatch:",
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"[OUTPUT_BLIF] Vector 27 mismatch:",
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"[OUTPUT_BLIF] Vector 28 mismatch:",
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"[OUTPUT_BLIF] Vector 29 mismatch:",
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"[OUTPUT_BLIF] Vector 30 mismatch:",
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"[OUTPUT_BLIF] Vector 32 mismatch:",
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"[OUTPUT_BLIF] Vector 33 mismatch:",
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"[OUTPUT_BLIF] Vector 34 mismatch:",
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"[OUTPUT_BLIF] Vector 35 mismatch:",
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"[OUTPUT_BLIF] Vector 36 mismatch:",
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"[OUTPUT_BLIF] Vector 37 mismatch:"
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]
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},
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"DEFAULT": {
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"test_name": "n/a",
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"architecture": "n/a",

‎ODIN_II/regression_test/benchmark/task/keywords/defparam/synthesis_result.json

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"defparam/defparam_depth_2/no_arch": {
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"test_name": "defparam/defparam_depth_2/no_arch",
8888
"verilog": "defparam_depth_2.v",
89-
"exit": 134,
90-
"errors": [
91-
"defparam_depth_2.v:16:1 [NETLIST] This module port simple_op.m2^in~2 is unused in module assg1"
92-
]
89+
"warnings": [
90+
"defparam_depth_2.v:16:3 [NETLIST] This module port in2[2] is unused in module assg1",
91+
"defparam_depth_2.v:16:3 [NETLIST] This module port in2[3] is unused in module assg1",
92+
"defparam_depth_2.v:16:3 [NETLIST] This module port in2[4] is unused in module assg1",
93+
"defparam_depth_2.v:16:3 [NETLIST] This module port in2[5] is unused in module assg1",
94+
"defparam_depth_2.v:16:3 [NETLIST] This module port in2[6] is unused in module assg1",
95+
"defparam_depth_2.v:16:3 [NETLIST] This module port in2[7] is unused in module assg1",
96+
"defparam_depth_2.v:8:4 [NETLIST] This output is undriven (simple_op^out2~2) and will be removed",
97+
"defparam_depth_2.v:8:4 [NETLIST] This output is undriven (simple_op^out2~3) and will be removed",
98+
"defparam_depth_2.v:8:4 [NETLIST] This output is undriven (simple_op^out2~4) and will be removed",
99+
"defparam_depth_2.v:8:4 [NETLIST] This output is undriven (simple_op^out2~5) and will be removed",
100+
"defparam_depth_2.v:8:4 [NETLIST] This output is undriven (simple_op^out2~6) and will be removed",
101+
"defparam_depth_2.v:8:4 [NETLIST] This output is undriven (simple_op^out2~7) and will be removed",
102+
"defparam_depth_2.v:8:4 [NETLIST] Net simple_op.m2^out~2 driving node simple_op^out2~2 is itself undriven.",
103+
"defparam_depth_2.v:8:4 [NETLIST] Net simple_op.m2^out~3 driving node simple_op^out2~3 is itself undriven.",
104+
"defparam_depth_2.v:8:4 [NETLIST] Net simple_op.m2^out~4 driving node simple_op^out2~4 is itself undriven.",
105+
"defparam_depth_2.v:8:4 [NETLIST] Net simple_op.m2^out~5 driving node simple_op^out2~5 is itself undriven.",
106+
"defparam_depth_2.v:8:4 [NETLIST] Net simple_op.m2^out~6 driving node simple_op^out2~6 is itself undriven.",
107+
"defparam_depth_2.v:8:4 [NETLIST] Net simple_op.m2^out~7 driving node simple_op^out2~7 is itself undriven."
108+
],
109+
"Pi": 4,
110+
"Po": 10,
111+
"Longest Path": 2,
112+
"Average Path": 1
93113
},
94114
"defparam/defparam_simple_failure/no_arch": {
95115
"test_name": "defparam/defparam_simple_failure/no_arch",

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