Odin: include new benchmarks

Author: emacdo12

ODIN_II/regression_test/benchmark/task/fpu/hard_logic/task.conf

@@ -0,0 +1,29 @@
+########################
+# arch benchmarks config
+########################
+
+script_synthesis_params=--time_limit 3600s 
+simulation_params= -g 2 -L reset rst -H we
+script_simulation_params=--time_limit 3600s
+
+# Path to directory of circuits to use
+circuits_dir=../vtr_flow/benchmarks/fpu/hardlogic
+
+# Path to directory of architectures to use
+archs_dir=../vtr_flow/arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=bfly.v
+circuit_list_add=bgm.v
+circuit_list_add=dscg.v
+circuit_list_add=fir.v
+circuit_list_add=mm3.v
+circuit_list_add=ode.v
+circuit_list_add=syn2.v
+circuit_list_add=syn7.v
+
+# Add architectures to list to sweep
+arch_list_add=hard_fpu_arch_timing.xml
+
+synthesis_parse_file=regression_test/parse_result/conf/synth.toml
+simulation_parse_file=regression_test/parse_result/conf/sim.toml

ODIN_II/regression_test/benchmark/task/fpu/soft_logic/task.conf

@@ -0,0 +1,26 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=../vtr_flow/benchmarks/fpu/softlogic
+
+# Path to directory of architectures to use
+archs_dir=../vtr_flow/arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=bfly.v
+circuit_list_add=bgm.v
+circuit_list_add=dscg.v
+circuit_list_add=fir.v
+circuit_list_add=mm3.v
+circuit_list_add=ode.v
+circuit_list_add=syn2.v
+circuit_list_add=syn7.v
+
+# Add architectures to list to sweep
+arch_list_add=k6_N10_mem32K_40nm.xml
+
+synthesis_parse_file=regression_test/parse_result/conf/synth.toml
+simulation_parse_file=regression_test/parse_result/conf/sim.toml

ODIN_II/regression_test/benchmark/verilog/syntax/bm_unused_input_pins.v

@@ -0,0 +1,19 @@
+/* This test checks that when you pass an input into a function and there are unused Odin doesn't fail but throws a warning */
+
+module func(in,out);
+    input  [7:0] in;
+    output [3:0] out;
+
+    assign out = in[3:0];
+endmodule 
+
+module simple_op(in_1,out_1);
+    input  [7:0] in_1;
+    output [7:0] out_1;
+
+    func m1(
+        .in  (in_1),
+        .out (out_1)
+    );
+endmodule 
+

ODIN_II/regression_test/benchmark/verilog/syntax/bm_unused_input_pins_input

@@ -0,0 +1,39 @@
+GLOBAL_SIM_BASE_CLK in_1
+1 0X9e
+0 0X1a
+1 0X1a
+0 0Xc7
+1 0X7a
+0 0X54
+1 0X71
+0 0Xba
+1 0Xa5
+0 0Xb0
+1 0X08
+0 0X71
+1 0Xc8
+0 0Xfa
+1 0X6f
+0 0Xa6
+1 0X51
+0 0X7a
+1 0X0a
+0 0X7d
+1 0X5b
+0 0Xcf
+1 0X39
+0 0X70
+1 0X55
+0 0X13
+1 0X93
+0 0Xd0
+1 0X04
+0 0X20
+1 0Xcc
+0 0Xe5
+1 0X4e
+0 0X80
+1 0X8a
+0 0X68
+1 0X6f
+0 0X05

ODIN_II/regression_test/benchmark/verilog/syntax/bm_unused_input_pins_output

@@ -0,0 +1,39 @@
+out_1
+0Xe
+0Xa
+0Xa
+0X7
+0Xa
+0X4
+0X1
+0Xa
+0X5
+0X0
+0X8
+0X1
+0X8
+0Xa
+0Xf
+0X6
+0X1
+0Xa
+0Xa
+0Xd
+0Xb
+0Xf
+0X9
+0X0
+0X5
+0X3
+0X3
+0X0
+0X4
+0X0
+0Xc
+0X5
+0Xe
+0X0
+0Xa
+0X8
+0Xf
+0X5