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call edge_delay() instead of accessing switch delay
1 parent df6062c commit dd1df5c

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9 files changed

+47
-36
lines changed

9 files changed

+47
-36
lines changed

libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -70,8 +70,6 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
7070
enum e_base_cost_type base_cost_type,
7171
const bool echo_enabled,
7272
const char* echo_file_name) {
73-
int length, i, index;
74-
7573
(void)segment_inf;
7674
int total_num_segment = segment_inf_x.size() + segment_inf_y.size();
7775
/*CHAX & CHANY segment lsit sizes may differ. but if we're using uniform channels, they
@@ -85,7 +83,7 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
8583
* * other than base_cost are invalid. Mark invalid fields as OPEN for safety. */
8684

8785
constexpr float nan = std::numeric_limits<float>::quiet_NaN();
88-
for (i = SOURCE_COST_INDEX; i <= IPIN_COST_INDEX; i++) {
86+
for (int i = SOURCE_COST_INDEX; i <= IPIN_COST_INDEX; i++) {
8987
rr_indexed_data[RRIndexedDataId(i)].ortho_cost_index = OPEN;
9088
rr_indexed_data[RRIndexedDataId(i)].seg_index = OPEN;
9189
rr_indexed_data[RRIndexedDataId(i)].inv_length = nan;
@@ -116,10 +114,11 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
116114
/* X-directed segments*/
117115

118116
for (size_t iseg = 0; iseg < segment_inf_x.size(); ++iseg) {
119-
index = iseg + CHANX_COST_INDEX_START;
117+
int index = iseg + CHANX_COST_INDEX_START;
120118

121119
rr_indexed_data[RRIndexedDataId(index)].ortho_cost_index = ortho_costs[iseg];
122120

121+
int length;
123122
if (segment_inf_x[iseg].longline)
124123
length = grid.width();
125124
else
@@ -134,9 +133,10 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
134133
/* Y-directed segments*/
135134

136135
for (size_t iseg = segment_inf_x.size(); iseg < ortho_costs.size(); ++iseg) {
137-
index = iseg + CHANX_COST_INDEX_START;
136+
int index = iseg + CHANX_COST_INDEX_START;
138137
rr_indexed_data[RRIndexedDataId(index)].ortho_cost_index = ortho_costs[iseg];
139138

139+
int length;
140140
if (segment_inf_x[iseg - segment_inf_x.size()].longline)
141141
length = grid.width();
142142
else
@@ -171,8 +171,8 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
171171
* a copy passed to the function to store the index w.r.t the parallel axis segment list.*/
172172

173173
std::vector<int> find_ortho_cost_index(const RRGraphView& rr_graph,
174-
const std::vector<t_segment_inf> segment_inf_x,
175-
const std::vector<t_segment_inf> segment_inf_y,
174+
const std::vector<t_segment_inf>& segment_inf_x,
175+
const std::vector<t_segment_inf>& segment_inf_y,
176176
e_parallel_axis parallel_axis) {
177177
auto segment_inf_parallel = parallel_axis == X_AXIS ? segment_inf_x : segment_inf_y;
178178
auto segment_inf_perp = parallel_axis == X_AXIS ? segment_inf_y : segment_inf_x;
@@ -671,7 +671,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph,
671671
}
672672

673673
avg_switch_R += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).R;
674-
avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel;
674+
avg_switch_T += rr_graph.edge_delay(edge);
675675
avg_switch_Cinternal += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cinternal;
676676

677677
if (buffered == UNDEFINED) {

libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,8 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph,
1818
const char* echo_file_name);
1919

2020
std::vector<int> find_ortho_cost_index(const RRGraphView& rr_graph,
21-
const std::vector<t_segment_inf> segment_inf_x,
22-
const std::vector<t_segment_inf> segment_inf_y,
21+
const std::vector<t_segment_inf>& segment_inf_x,
22+
const std::vector<t_segment_inf>& segment_inf_y,
2323
e_parallel_axis parallel_axis);
2424

2525
#endif

vpr/src/route/connection_router.cpp

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -702,7 +702,10 @@ void ConnectionRouter<Heap>::evaluate_timing_driven_node_costs(RTExploredNode* t
702702
bool switch_buffered = rr_switch_inf_[iswitch].buffered();
703703
bool reached_configurably = rr_switch_inf_[iswitch].configurable();
704704
float switch_R = rr_switch_inf_[iswitch].R;
705-
float switch_Tdel = rr_switch_inf_[iswitch].Tdel;
705+
// Instead of looking up the delay from the RR switch type info,
706+
// we call edge_delay() method that returns the exact delay calculated
707+
// by adding edge-specific delays to the nominal delay of switch type
708+
float switch_Tdel = rr_graph_->edge_delay(to->prev_edge);
706709
float switch_Cinternal = rr_switch_inf_[iswitch].Cinternal;
707710

708711
//To node info

vpr/src/route/route_tree.cpp

Lines changed: 7 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -184,7 +184,7 @@ void RouteTree::reload_timing(vtr::optional<RouteTreeNode&> from_node) {
184184
}
185185

186186
void RouteTree::reload_timing_unlocked(vtr::optional<RouteTreeNode&> from_node) {
187-
auto& device_ctx = g_vpr_ctx.device();
187+
const auto& device_ctx = g_vpr_ctx.device();
188188
const auto& rr_graph = device_ctx.rr_graph;
189189

190190
if (!from_node)
@@ -208,6 +208,7 @@ void RouteTree::reload_timing_unlocked(vtr::optional<RouteTreeNode&> from_node)
208208
/* TODO Just a note (no action needed for this PR): In future, we need to consider APIs that returns
209209
* the Tdel for a routing trace in RRGraphView.*/
210210
Tdel_start += rr_graph.rr_switch_inf(iswitch).R * unbuffered_subtree_rt_root.C_downstream;
211+
// TODO: probably call edge_delay() to retrieve the per-edge delay instead of per switch type delay
211212
Tdel_start += rr_graph.rr_switch_inf(iswitch).Tdel;
212213
}
213214

@@ -325,23 +326,23 @@ RouteTree::update_unbuffered_ancestors_C_downstream(RouteTreeNode& from_node) {
325326
* must be correct before this routine is called. Tarrival is the time at
326327
* at which the signal arrives at this node's *input*. */
327328
void RouteTree::load_route_tree_Tdel(RouteTreeNode& from_node, float Tarrival) {
328-
auto& device_ctx = g_vpr_ctx.device();
329+
const auto& device_ctx = g_vpr_ctx.device();
329330
const auto& rr_graph = device_ctx.rr_graph;
330331

331332
RRNodeId inode = from_node.inode;
332-
float Tdel, Tchild;
333333

334334
/* Assuming the downstream connections are, on average, connected halfway
335335
* along a wire segment's length. See discussion in net_delay.cpp if you want
336336
* to change this. */
337-
Tdel = Tarrival + 0.5 * from_node.C_downstream * rr_graph.node_R(inode);
338-
from_node.Tdel = Tdel;
337+
from_node.Tdel = Tarrival + 0.5 * from_node.C_downstream * rr_graph.node_R(inode);
339338

340339
/* Now expand the children of this node to load their Tdel values */
341340
for (RouteTreeNode& child : from_node._child_nodes()) {
342341
RRSwitchId iswitch = child.parent_switch;
343342

344-
Tchild = Tdel + rr_graph.rr_switch_inf(iswitch).R * child.C_downstream;
343+
float Tchild = from_node.Tdel + rr_graph.rr_switch_inf(iswitch).R * child.C_downstream;
344+
// TODO: we should probably look up the per-edge delay instead of switch type delay
345+
// For this, we need to add a new member variable to RouteTreeNode to record it parent edge
345346
Tchild += rr_graph.rr_switch_inf(iswitch).Tdel; /* Intrinsic switch delay. */
346347
load_route_tree_Tdel(child, Tchild);
347348
}

vpr/src/route/router_lookahead_map_utils.cpp

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -166,15 +166,16 @@ PQ_Entry::PQ_Entry(RRNodeId set_rr_node, int /*switch_ind*/, float parent_delay,
166166
this->cost = this->delay;
167167
}
168168

169-
PQ_Entry_Delay::PQ_Entry_Delay(
170-
RRNodeId set_rr_node,
171-
int switch_ind,
172-
const PQ_Entry_Delay* parent) {
169+
PQ_Entry_Delay::PQ_Entry_Delay(RRNodeId set_rr_node,
170+
int switch_ind,
171+
const PQ_Entry_Delay* parent) {
173172
this->rr_node = set_rr_node;
174173

175174
if (parent != nullptr) {
176-
auto& device_ctx = g_vpr_ctx.device();
175+
const auto& device_ctx = g_vpr_ctx.device();
177176
const auto& rr_graph = device_ctx.rr_graph;
177+
// We use nominal switch delay instead of per-edge delay that can be retrieved
178+
// by calling edge_delay() method
178179
float Tsw = rr_graph.rr_switch_inf(RRSwitchId(switch_ind)).Tdel;
179180
float Rsw = rr_graph.rr_switch_inf(RRSwitchId(switch_ind)).R;
180181
float Cnode = rr_graph.node_C(set_rr_node);
@@ -1019,6 +1020,8 @@ static void dijkstra_flood_to_wires(int itile,
10191020

10201021
for (RREdgeId edge : rr_graph.edge_range(curr.node)) {
10211022
int iswitch = rr_graph.rr_nodes().edge_switch(edge);
1023+
// We use nominal switch delay instead of per-edge delay that can be retrieved
1024+
// by calling edge_delay() method
10221025
float incr_delay = rr_graph.rr_switch_inf(RRSwitchId(iswitch)).Tdel;
10231026

10241027
RRNodeId next_node = rr_graph.rr_nodes().edge_sink_node(edge);
@@ -1122,6 +1125,8 @@ static void dijkstra_flood_to_ipins(RRNodeId node, util::t_chan_ipins_delays& ch
11221125

11231126
for (RREdgeId edge : rr_graph.edge_range(curr.node)) {
11241127
int iswitch = rr_graph.rr_nodes().edge_switch(edge);
1128+
// We use nominal switch delay instead of per-edge delay that can be retrieved
1129+
// by calling edge_delay() method
11251130
float new_delay = rr_graph.rr_switch_inf(RRSwitchId(iswitch)).Tdel;
11261131

11271132
RRNodeId next_node = rr_graph.rr_nodes().edge_sink_node(edge);
@@ -1262,6 +1267,8 @@ static void run_intra_tile_dijkstra(const RRGraphView& rr_graph,
12621267
auto cost_index = rr_graph.node_cost_index(next_node);
12631268
int iswitch = rr_graph.rr_nodes().edge_switch(edge);
12641269

1270+
// We use nominal switch delay instead of per-edge delay that can be retrieved
1271+
// by calling edge_delay() method
12651272
float incr_delay = rr_graph.rr_switch_inf(RRSwitchId(iswitch)).Tdel;
12661273
float incr_cong = device_ctx.rr_indexed_data[cost_index].base_cost;
12671274

vpr/src/route/rr_graph.cpp

Lines changed: 5 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -678,7 +678,7 @@ static void add_pin_chain(const std::vector<int>& pin_chain,
678678
bool is_new_chain);
679679

680680
/***
681-
* @brief Return a pair. The firt element indicates whether the switch is added or it was already added. The second element is the switch index.
681+
* @brief Return a pair. The first element indicates whether the switch is added or it was already added. The second element is the switch index.
682682
* @param rr_graph
683683
* @param arch_sw_inf
684684
* @param R_minW_nmos Needs to be passed to use create_rr_switch_from_arch_switch
@@ -1838,11 +1838,11 @@ static void load_rr_switch_inf(RRGraphBuilder& rr_graph_builder,
18381838
}
18391839
}
18401840
}
1841+
18411842
/* This function creates a routing switch for the usage of routing resource graph, based on a routing switch defined in architecture file.
18421843
*
18431844
* Since users can specify a routing switch whose buffer size is automatically tuned for routing architecture, the function here sets a definite buffer size, as required by placers and routers.
18441845
*/
1845-
18461846
t_rr_switch_inf create_rr_switch_from_arch_switch(const t_arch_switch_inf& arch_sw_inf,
18471847
const float R_minW_nmos,
18481848
const float R_minW_pmos) {
@@ -5103,11 +5103,11 @@ static std::pair<bool, int> find_create_intra_cluster_sw(RRGraphBuilder& rr_grap
51035103
float R_minW_pmos,
51045104
bool is_rr_sw,
51055105
float delay) {
5106-
const auto& rr_graph_switches = rr_graph.rr_switch();
5106+
const vtr::vector<RRSwitchId, t_rr_switch_inf>& rr_graph_switches = rr_graph.rr_switch();
51075107

51085108
if (is_rr_sw) {
51095109
for (int rr_switch_id = 0; rr_switch_id < (int)rr_graph_switches.size(); rr_switch_id++) {
5110-
const auto& rr_sw = rr_graph_switches[RRSwitchId(rr_switch_id)];
5110+
const t_rr_switch_inf& rr_sw = rr_graph_switches[RRSwitchId(rr_switch_id)];
51115111
if (rr_sw.intra_tile) {
51125112
if (rr_sw.Tdel == delay) {
51135113
return std::make_pair(false, rr_switch_id);
@@ -5126,11 +5126,7 @@ static std::pair<bool, int> find_create_intra_cluster_sw(RRGraphBuilder& rr_grap
51265126
auto find_res = std::find_if(arch_sw_inf.begin(), arch_sw_inf.end(),
51275127
[delay](const std::pair<int, t_arch_switch_inf>& sw_inf_pair) {
51285128
const t_arch_switch_inf& sw_inf = std::get<1>(sw_inf_pair);
5129-
if (sw_inf.intra_tile && sw_inf.Tdel() == delay) {
5130-
return true;
5131-
} else {
5132-
return false;
5133-
}
5129+
return sw_inf.intra_tile && sw_inf.Tdel() == delay;
51345130
});
51355131

51365132
// There isn't any other intra-tile edge with the same delay - Create a new one!

vpr/src/route/rr_graph2.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder,
6060
int* index);
6161

6262
static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder,
63-
const std::vector<int> conn_tracks,
63+
const std::vector<int>& conn_tracks,
6464
const int layer,
6565
const int to_chan,
6666
const int to_seg,
@@ -2168,7 +2168,7 @@ void alloc_and_load_tile_rr_node_indices(RRGraphBuilder& rr_graph_builder,
21682168
}
21692169

21702170
static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder,
2171-
const std::vector<int> conn_tracks,
2171+
const std::vector<int>& conn_tracks,
21722172
const int layer,
21732173
const int to_chan,
21742174
const int to_seg,

vpr/src/util/vpr_utils.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2019,10 +2019,14 @@ float get_min_cross_layer_delay() {
20192019
const auto& rr_graph = g_vpr_ctx.device().rr_graph;
20202020
float min_delay = std::numeric_limits<float>::max();
20212021

2022-
for (const auto& driver_node : rr_graph.nodes()) {
2022+
for (const RRNodeId driver_node : rr_graph.nodes()) {
20232023
for (size_t edge_id = 0; edge_id < rr_graph.num_edges(driver_node); edge_id++) {
2024-
const auto& sink_node = rr_graph.edge_sink_node(driver_node, edge_id);
2024+
const RRNodeId sink_node = rr_graph.edge_sink_node(driver_node, edge_id);
20252025
if (rr_graph.node_layer(driver_node) != rr_graph.node_layer(sink_node)) {
2026+
// Instead of calling edge_delay() method, we retrieve the delay from the switch type
2027+
// that the edge represents. Since the minimum delay returned by this function is used
2028+
// to construct the router lookahead, it is better nominal switch delays instead of exact
2029+
// ones that are calculated by adding edge-specific offsets.
20262030
int i_switch = rr_graph.edge_switch(driver_node, edge_id);
20272031
float edge_delay = rr_graph.rr_switch_inf(RRSwitchId(i_switch)).Tdel;
20282032
min_delay = std::min(min_delay, edge_delay);

vpr/src/util/vpr_utils.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -329,7 +329,7 @@ void apply_route_constraints(const UserRouteConstraints& constraint);
329329
/**
330330
* @brief Iterate over all inter-layer switch types and return the minimum delay of it.
331331
* useful four router lookahead to to have some estimate of the cost of crossing a layer
332-
* @return
332+
* @return The minimum delay of goring through an inter-layer switch.
333333
*/
334334
float get_min_cross_layer_delay();
335335

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