fix simulation directory missing trailing slash

Author: jeanlego

ODIN_II/SRC/odin_ii.cpp

@@ -69,7 +69,7 @@ OTHER DEALINGS IN THE SOFTWARE.
 #include "vtr_path.h"
 #include "vtr_memory.h"
 
-#define DEFAULT_OUTPUT "temp/"
+#define DEFAULT_OUTPUT "temp"
 
 size_t current_parse_file;
 t_arch Arch;

ODIN_II/SRC/simulate_blif.cpp

@@ -344,28 +344,28 @@ sim_data_t *init_simulation(netlist_t *netlist)
 
 	// Open the output vector file.
 	char out_vec_file[128] = { 0 };
-	odin_sprintf(out_vec_file,"%s%s",((char *)global_args.sim_directory),OUTPUT_VECTOR_FILE_NAME);
+	odin_sprintf(out_vec_file,"%s/%s",((char *)global_args.sim_directory),OUTPUT_VECTOR_FILE_NAME);
 	sim_data->out = fopen(out_vec_file, "w");
 	if (!sim_data->out)
 		error_message(SIMULATION_ERROR, 0, -1, "Could not create output vector file.");
 
 	// Open the input vector file.
 	char in_vec_file[128] = { 0 };
-	odin_sprintf(in_vec_file,"%s%s",((char *)global_args.sim_directory),INPUT_VECTOR_FILE_NAME);
+	odin_sprintf(in_vec_file,"%s/%s",((char *)global_args.sim_directory),INPUT_VECTOR_FILE_NAME);
 	sim_data->in_out = fopen(in_vec_file, "w+");
 	if (!sim_data->in_out)
 		error_message(SIMULATION_ERROR, 0, -1, "Could not create input vector file.");
 
 	// Open the activity output file.
 	char act_file[128] = { 0 };
-	odin_sprintf(act_file,"%s%s",((char *)global_args.sim_directory),OUTPUT_ACTIVITY_FILE_NAME);
+	odin_sprintf(act_file,"%s/%s",((char *)global_args.sim_directory),OUTPUT_ACTIVITY_FILE_NAME);
 	sim_data->act_out = fopen(act_file, "w");
 	if (!sim_data->act_out)
 		error_message(SIMULATION_ERROR, 0, -1, "Could not create activity output file.");
 
 	// Open the modelsim vector file.
 	char test_file[128] = { 0 };
-	odin_sprintf(test_file,"%s%s",((char *)global_args.sim_directory),MODEL_SIM_FILE_NAME);
+	odin_sprintf(test_file,"%s/%s",((char *)global_args.sim_directory),MODEL_SIM_FILE_NAME);
 	sim_data->modelsim_out = fopen(test_file, "w");
 	if (!sim_data->modelsim_out)
 		error_message(SIMULATION_ERROR, 0, -1, "Could not create modelsim output file.");
@@ -3115,7 +3115,7 @@ static int verify_output_vectors(char* output_vector_file, int num_vectors)
 
 		// Our current output vectors. (Just produced.)
 		char out_vec_file[128] = { 0 };
-		odin_sprintf(out_vec_file,"%s%s",((char *)global_args.sim_directory),OUTPUT_VECTOR_FILE_NAME);
+		odin_sprintf(out_vec_file,"%s/%s",((char *)global_args.sim_directory),OUTPUT_VECTOR_FILE_NAME);
 		FILE *current_out  = fopen(out_vec_file, "r");
 		if (!current_out)
 			error_message(SIMULATION_ERROR, 0, -1, "Could not open output vector file.");

ODIN_II/verify_odin.sh

@@ -248,14 +248,39 @@ function sim() {
 				#build commands
 				mkdir -p $DIR
 
-				verilog_command="./wrapper_odin.sh --log_file ${DIR}/synthesis.log --test_name ${TEST_FULL_REF} --failure_log ${global_synthesis_failure}.log --time_limit ${TIME_LIMIT} ${USING_LOW_RESSOURCE}"
-				verilog_command="${verilog_command} ${DEFAULT_CMD_PARAM} ${arch_cmd} -V ${verilog_file} -o ${blif_file} -sim_dir ${DIR}/"
+verilog_command="\./wrapper_odin.sh \
+--log_file ${DIR}/synthesis.log \
+--test_name ${TEST_FULL_REF} \
+--failure_log ${global_synthesis_failure}.log \
+--time_limit ${TIME_LIMIT} \
+${USING_LOW_RESSOURCE} \
+${RUN_WITH_VALGRIND}"
+
+verilog_command="${verilog_command} \
+${DEFAULT_CMD_PARAM} \
+${arch_cmd} \
+-V ${verilog_file} \
+-o ${blif_file} \
+-sim_dir ${DIR}"
+
 				echo "${verilog_command}" > ${DIR}/cmd_param
 
 				if [ "_$use_sim" == "_1" ]
 				then
-					simulation_command="./wrapper_odin.sh --log_file ${DIR}/simulation.log --test_name ${TEST_FULL_REF} --failure_log ${global_simulation_failure}.log --time_limit ${TIME_LIMIT} ${USING_LOW_RESSOURCE}"
-					simulation_command="${simulation_command} ${DEFAULT_CMD_PARAM} ${arch_cmd} -b ${blif_file} -sim_dir ${DIR}/"
+
+simulation_command="./wrapper_odin.sh \
+--log_file ${DIR}/simulation.log \
+--test_name ${TEST_FULL_REF} \
+--failure_log ${global_simulation_failure}.log \
+--time_limit ${TIME_LIMIT} \
+${USING_LOW_RESSOURCE} \
+${RUN_WITH_VALGRIND}"
+
+simulation_command="${simulation_command} \
+${DEFAULT_CMD_PARAM} \
+${arch_cmd} \
+-b ${blif_file} \
+-sim_dir ${DIR}"
 
 					if [ "_$with_input_vector" == "_1" ] && [ "_$REGENERATE_BENCH" != "_1" ]; then
 						simulation_command="${simulation_command} -t ${benchmark_dir}/${test_name}_input"
@@ -429,6 +454,9 @@ function parse_args() {
 				fi
 				shift
 				;;
+			--valgrind)
+				RUN_WITH_VALGRIND="--valgrind"
+				;;
 
 			--test)
 				if [ "_$TEST_TYPE" != "_" ]

ODIN_II/wrapper_odin.sh

@@ -156,7 +156,7 @@ do
 			;;
 
 		--valgrind)
-			VALGRIND_EXEC="valgrind"
+			VALGRIND_EXEC="valgrind --leak-check=full"
 			;;
 
 		*)