[Odin]: - fix mkDelayWorker32B dpram size bug in Odin benchmarks

	- regenerate expectation results of Odin/full test

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json

@@ -255,17 +255,17 @@
         "techmap_time(ms)": 45,
         "synthesis_time(ms)": 4208.9,
         "Latch Drivers": 1,
-        "Pi": 505,
+        "Pi": 510,
         "Po": 553,
-        "logic element": 13647,
+        "logic element": 13897,
         "latch": 2309,
         "Adder": 768,
-        "Memory": 1074,
+        "Memory": 1336,
         "generic logic size": 4,
         "Longest Path": 319,
         "Average Path": 4,
-        "Estimated LUTs": 13971,
-        "Total Node": 17799
+        "Estimated LUTs": 14663,
+        "Total Node": 18311
     },
     "large/mkSMAdapter4B/k6_frac_N10_frac_chain_mem32K_40nm": {
         "test_name": "large/mkSMAdapter4B/k6_frac_N10_frac_chain_mem32K_40nm",

ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json

@@ -286,17 +286,17 @@
         "techmap_time(ms)": 43.2,
         "synthesis_time(ms)": 4117.9,
         "Latch Drivers": 1,
-        "Pi": 505,
+        "Pi": 510,
         "Po": 553,
-        "logic element": 13647,
+        "logic element": 13897,
         "latch": 2309,
         "Adder": 768,
-        "Memory": 1074,
+        "Memory": 1336,
         "generic logic size": 4,
         "Longest Path": 319,
         "Average Path": 4,
-        "Estimated LUTs": 13971,
-        "Total Node": 17799
+        "Estimated LUTs": 14663,
+        "Total Node": 18311
     },
     "vtr/mkPktMerge/k6_frac_N10_frac_chain_mem32K_40nm": {
         "test_name": "vtr/mkPktMerge/k6_frac_N10_frac_chain_mem32K_40nm",

ODIN_II/regression_test/benchmark/verilog/large/mkDelayWorker32B.v

@@ -1523,8 +1523,8 @@ wire [255:0] dp_out_not_used2;
 //	  .DATA_WIDTH(32'b1056),
 //	  .MEMSIZE(11'b1024)) mesgWF_memory(
 
- defparam dpram1.ADDR_WIDTH = 10;
- defparam dpram1.DATA_WIDTH = 256;  
+ defparam dpram2.ADDR_WIDTH = 10;
+ defparam dpram2.DATA_WIDTH = 256;  
  dual_port_ram dpram2   (
 						.clk(wciS0_Clk),
 					    .addr1(mesgWF_memory__ADDRA),
@@ -6688,4 +6688,4 @@ always @(posedge clk )
 	else
 	if(re & (cnt <= (`max_size-`n+1)) & !we)	full_n_r <=  1'b0;
 
-endmodule
+endmodule