[Odin]: add -S/--tcl option to run Yosys in Odin-II

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

ODIN_II/SRC/YYosys.cpp

@@ -75,6 +75,11 @@ YYosys::YYosys() {
     /* create Yosys child process */
     if ((this->yosys_pid = fork()) < 0)
         error_message(UTIL, unknown_location, "%s", YOSYS_FORK_ERROR);
+    else {
+        /* set up VTR_ROOT path environment variable */
+        set_env("VTR_ROOT", std::string(global_args.program_root + "/..").c_str(), 1);
+    }
+
 #endif
 }
 
@@ -205,52 +210,57 @@ void YYosys::execute() {
     /* must only be performed in the Yosys child process */
     oassert(this->yosys_pid == 0);
 
-    // Read the hardware decription Verilog circuits
-    // FOR loop enables include feature for Yosys+Odin (multiple Verilog input files)
-    for (auto verilog_circuit : this->verilog_circuits)
-        run_pass(std::string("read_verilog -nomem2reg -nolatches " + verilog_circuit));
-
-    // Check whether cells match libraries and find top module
-    run_pass(std::string("hierarchy -check -auto-top"));
-
-    // Use a readable name convention
-    run_pass(std::string("autoname"));
-    // Translate processes to netlist components such as MUXs, FFs and latches
-    run_pass(std::string("proc; opt;"));
-    // Extraction and optimization of finite state machines
-    run_pass(std::string("fsm; opt;"));
-    // Collects memories, their port and create multiport memory cells
-    run_pass(std::string("memory_collect; memory_dff; opt;"));
-
-    // Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
-    run_pass(std::string("check"));
-    // Transform asynchronous dffs to synchronous dffs using techlib files provided by Yosys
-    run_pass(std::string("techmap -map " + this->odin_techlib + "/adff2dff.v"));
-    run_pass(std::string("techmap -map " + this->odin_techlib + "/adffe2dff.v"));
-
-    /**
-     * convert yosys mem blocks to BRAMs / ROMs
-     *
-     * [NOTE] : Yosys complains about expression width more than 24 bits.
-     * E.g.[63 : 0] memory[18 : 0] == > ERROR : Expression width 33554432 exceeds implementation limit of 16777216 !
-     * Therfore, Yosys internal memory cells will be handled inside Odin-II as YMEM cell type.
-     *
-     * The following commands transform Yosys internal memories into BRAMs/ROMs defined in the Odin-II techlib
-     * However, due to the above-mentioned reason they are commented.
-     *  Yosys::run_pass(std::string("memory_bram -rules ", this->odin_techlib, "/mem_rules.txt"))
-     *  Yosys::run_pass(std::string("techmap -map ", this->odin_techlib, "/mem_map.v"));
-     */
-
-    // Transform the design into a new one with single top module
-    run_pass(std::string("flatten"));
-    // Transforms PMUXes into trees of regular multiplexers
-    run_pass(std::string("pmuxtree"));
-    // "-undirven" to ensure there is no wire without drive
-    run_pass(std::string("opt -undriven -full")); // -noff #potential option to remove all sdffXX and etc. Only dff will remain
-    // Use a readable name convention
-    run_pass(std::string("autoname"));
-    // Print statistics
-    run_pass(std::string("stat"));
+    if (configuration.tcl_file != "") {
+        // run the tcl file by yosys
+        run_pass(std::string("tcl " + configuration.tcl_file));
+    } else {
+        // Read the hardware decription Verilog circuits
+        // FOR loop enables include feature for Yosys+Odin (multiple Verilog input files)
+        for (auto verilog_circuit : this->verilog_circuits)
+            run_pass(std::string("read_verilog -nomem2reg -nolatches " + verilog_circuit));
+
+        // Check whether cells match libraries and find top module
+        run_pass(std::string("hierarchy -check -auto-top"));
+
+        // Use a readable name convention
+        run_pass(std::string("autoname"));
+        // Translate processes to netlist components such as MUXs, FFs and latches
+        run_pass(std::string("proc; opt;"));
+        // Extraction and optimization of finite state machines
+        run_pass(std::string("fsm; opt;"));
+        // Collects memories, their port and create multiport memory cells
+        run_pass(std::string("memory_collect; memory_dff; opt;"));
+
+        // Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
+        run_pass(std::string("check"));
+        // Transform asynchronous dffs to synchronous dffs using techlib files provided by Yosys
+        run_pass(std::string("techmap -map " + this->odin_techlib + "/adff2dff.v"));
+        run_pass(std::string("techmap -map " + this->odin_techlib + "/adffe2dff.v"));
+
+        /**
+         * convert yosys mem blocks to BRAMs / ROMs
+         *
+         * [NOTE] : Yosys complains about expression width more than 24 bits.
+         * E.g.[63 : 0] memory[18 : 0] == > ERROR : Expression width 33554432 exceeds implementation limit of 16777216 !
+         * Therfore, Yosys internal memory cells will be handled inside Odin-II as YMEM cell type.
+         *
+         * The following commands transform Yosys internal memories into BRAMs/ROMs defined in the Odin-II techlib
+         * However, due to the above-mentioned reason they are commented.
+         *  Yosys::run_pass(std::string("memory_bram -rules ", this->odin_techlib, "/mem_rules.txt"))
+         *  Yosys::run_pass(std::string("techmap -map ", this->odin_techlib, "/mem_map.v"));
+         */
+
+        // Transform the design into a new one with single top module
+        run_pass(std::string("flatten"));
+        // Transforms PMUXes into trees of regular multiplexers
+        run_pass(std::string("pmuxtree"));
+        // "-undirven" to ensure there is no wire without drive
+        run_pass(std::string("opt -undriven -full")); // -noff #potential option to remove all sdffXX and etc. Only dff will remain
+        // Use a readable name convention
+        run_pass(std::string("autoname"));
+        // Print statistics
+        run_pass(std::string("stat"));
+    }
 
 #endif
 }

ODIN_II/SRC/include/YYosys.hpp

@@ -44,6 +44,13 @@
 
 #include "odin_globals.h" // global_args
 
+/* to set local environment variable */
+#ifdef WIN32
+#    define set_env _setenv
+#else
+#    define set_env setenv
+#endif
+
 /**
  * @brief A class to provide the general object of Yosys synthezier
  */

ODIN_II/SRC/include/config_t.h

@@ -52,6 +52,7 @@ struct config_t {
     int soft_logic_memory_width_threshold;
 
     std::string arch_file; // Name of the FPGA architecture file
+    std::string tcl_file;  // TCL file to be run by yosys
 };
 
 extern config_t configuration;

ODIN_II/SRC/include/odin_types.h

@@ -96,8 +96,9 @@ struct global_args_t {
     argparse::ArgValue<std::string> blif_file;
     argparse::ArgValue<std::string> output_file;
     argparse::ArgValue<std::string> arch_file;   // Name of the FPGA architecture file
+    argparse::ArgValue<std::string> tcl_file;    // TCL file to be run by yosys elaborator
     argparse::ArgValue<std::string> elaborator;  // Name of the external elaborator tool, currently Yosys is supported, default is Odin
-    argparse::ArgValue<bool> permissive;         //turn possible_errors into warnings
+    argparse::ArgValue<bool> permissive;         // turn possible_errors into warnings
     argparse::ArgValue<bool> print_parse_tokens; // print the tokens as they are parsed byt the parser
 
     argparse::ArgValue<std::string> high_level_block; //Legacy option, no longer used

ODIN_II/SRC/odin_ii.cpp

@@ -344,7 +344,7 @@ netlist_t* start_odin_ii(int argc, char** argv) {
     printf("Using Lut input width of: %d\n", physical_lut_size);
 
     /* do High level Synthesis */
-    if (!configuration.list_of_file_names.empty()) {
+    if (!configuration.list_of_file_names.empty() || !configuration.tcl_file.empty()) {
         ODIN_ERROR_CODE error_code;
 
         print_input_files_info();
@@ -481,7 +481,7 @@ void get_options(int argc, char** argv) {
     get_current_path();
     // get Odin-II program name
     global_args.program_name = parser.prog();
-    // getting Odin-II path and program name
+    // getting Odin-II path
     global_args.program_root = get_directory(std::string(argv[0]));
 
     auto& input_grp = parser.add_argument_group("input files");
@@ -525,6 +525,14 @@ void get_options(int argc, char** argv) {
         .action(argparse::Action::STORE_TRUE)
         .metavar("INPUT_BLIF_FLATNESS");
 
+    ext_elaborator_group.add_argument(global_args.tcl_file, "-S")
+        .help("TCL file")
+        .metavar("TCL_FILE");
+
+    ext_elaborator_group.add_argument(global_args.tcl_file, "--tcl")
+        .help("TCL file")
+        .metavar("TCL_FILE");
+
     auto& other_grp = parser.add_argument_group("other options");
 
     other_grp.add_argument(global_args.show_help, "-h")
@@ -699,10 +707,11 @@ void get_options(int argc, char** argv) {
     if (!only_one_is_true({
             global_args.config_file.provenance() == argparse::Provenance::SPECIFIED, //have a config file
             global_args.blif_file.provenance() == argparse::Provenance::SPECIFIED,   //have a BLIF file
+            global_args.tcl_file.provenance() == argparse::Provenance::SPECIFIED,    //have a TCL file that includes HDL designs
             global_args.verilog_files.value().size() > 0                             //have a Verilog input list
         })) {
         parser.print_usage();
-        warning_message(PARSE_ARGS, unknown_location, "%s", "Must include only one of either:\n\ta config file(-c)\n\ta BLIF file(-b)\n\ta Verilog file(-V)\nUnless is used for infrastructure directly\n");
+        warning_message(PARSE_ARGS, unknown_location, "%s", "Must include only one of either:\n\ta config file(-c)\n\ta BLIF file(-b)\n\ta Verilog file(-V)\n\ta TCL file including HDL designs(-S)\nUnless is used for infrastructure directly\n");
     }
 
     //adjust thread count
@@ -735,6 +744,14 @@ void get_options(int argc, char** argv) {
         configuration.show_yosys_log = global_args.show_yosys_log;
     }
 
+    if (global_args.tcl_file.provenance() == argparse::Provenance::SPECIFIED) {
+        configuration.tcl_file = global_args.tcl_file;
+
+        coarsen_cleanup = true;
+        configuration.coarsen = true;
+        configuration.elaborator_type = elaborator_e::_YOSYS;
+    }
+
     if (global_args.write_netlist_as_dot.provenance() == argparse::Provenance::SPECIFIED) {
         configuration.output_netlist_graphs = global_args.write_netlist_as_dot;
     }
@@ -792,6 +809,7 @@ void set_default_config() {
     configuration.coarsen = false;
     configuration.fflegalize = false;
     configuration.show_yosys_log = false;
+    configuration.tcl_file = "";
     configuration.output_file_type = file_type_e::_BLIF;
     configuration.elaborator_type = elaborator_e::_ODIN;
     configuration.output_ast_graphs = 0;

ODIN_II/regression_test/tools/synth.tcl

@@ -1,12 +1,10 @@
 yosys -import
 
-# Read VTR baseline library first
-read_verilog -nomem2reg $env(PRIMITIVES);
-setattr -mod -set keep_hierarchy 1 single_port_ram;
-setattr -mod -set keep_hierarchy 1 dual_port_ram;
+# the environment variable VTR_ROOT is set by Odin-II.
+# Feel free to specify file paths using "$env(VTR_ROOT)/ ..." 
 
 # Read the hardware decription Verilog
-read_verilog -nomem2reg -nolatches $env(TCL_CIRCUIT);
+read_verilog -nomem2reg -nolatches $env(VTR_ROOT)/ODIN_II/regression_test/benchmark/verilog/common/mux.v;
 # Check that cells match libraries and find top module
 hierarchy -check -auto-top;
 
@@ -22,8 +20,8 @@ memory_collect; memory_dff; opt;
 # Looking for combinatorial loops, wires with multiple drivers and used wires without any driver.
 check;
 # resolve asynchronous dffs
-techmap -map $env(ODIN_TECHLIB)/adff2dff.v;
-techmap -map $env(ODIN_TECHLIB)/adffe2dff.v;
+techmap -map $env(VTR_ROOT)/ODIN_II/techlib/adff2dff.v;
+techmap -map $env(VTR_ROOT)/ODIN_II/techlib/adffe2dff.v;
 # convert mem block to bram/rom
 
 # [NOTE]: Yosys complains about expression width more than 24 bits.
@@ -42,9 +40,3 @@ opt -undriven -full; # -noff #potential option to remove all sdff and etc. Only
 autoname;
 # Print statistics
 stat;
-
-# param is to print non-standard cells attributes
-# impltf is also used not to show the definition of primary netlist ports, i.e. VCC, GND and PAD, in the output.
-write_blif -param -impltf $env(TCL_BLIF);
-
-exit;