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Odin: fix flip flop and memory timing issue
1 parent 8193e56 commit d373cee

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-163965
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199 files changed

+54352
-163965
lines changed

‎ODIN_II/SRC/adders.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -328,7 +328,7 @@ void add_the_blackbox_for_adds(FILE *out)
328328
/*-------------------------------------------------------------------------
329329
* (function: define_add_function)
330330
*-----------------------------------------------------------------------*/
331-
void define_add_function(nnode_t *node, short /*type*/, FILE *out)
331+
void define_add_function(nnode_t *node, FILE *out)
332332
{
333333
int i, j;
334334
int count;

‎ODIN_II/SRC/hard_blocks.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ t_model* find_hard_block(const char *name)
145145
return NULL;
146146
}
147147

148-
void define_hard_block(nnode_t *node, short /*type*/, FILE *out)
148+
void define_hard_block(nnode_t *node, FILE *out)
149149
{
150150
int i, j;
151151
int index, port;

‎ODIN_II/SRC/include/adders.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ extern void instantiate_hard_adder(nnode_t *node, short mark, netlist_t *netlist
6161
extern void instantiate_simple_soft_adder(nnode_t *node, short mark, netlist_t *netlist);
6262
extern void find_hard_adders();
6363
extern void add_the_blackbox_for_adds(FILE *out);
64-
extern void define_add_function(nnode_t *node, short type, FILE *out);
64+
extern void define_add_function(nnode_t *node, FILE *out);
6565
extern void split_adder(nnode_t *node, int a, int b, int sizea, int sizeb, int cin, int cout, int count, netlist_t *netlist);
6666
extern void iterate_adders(netlist_t *netlist);
6767
extern void clean_adders();

‎ODIN_II/SRC/include/hard_blocks.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,7 +31,7 @@ extern STRING_CACHE *hard_block_names;
3131
extern void register_hard_blocks();
3232
extern void deregister_hard_blocks();
3333
extern t_model* find_hard_block(const char *name);
34-
extern void define_hard_block(nnode_t *node, short type, FILE *out);
34+
extern void define_hard_block(nnode_t *node, FILE *out);
3535
extern void output_hard_blocks(FILE *out);
3636
extern int hard_block_port_size(t_model *hb, char *pname);
3737
extern enum PORTS hard_block_port_direction(t_model *hb, char *pname);

‎ODIN_II/SRC/include/multipliers.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ extern void instantiate_hard_multiplier(nnode_t *node, short mark, netlist_t *ne
4444
extern void instantiate_simple_soft_multiplier(nnode_t *node, short mark, netlist_t *netlist);
4545
extern void find_hard_multipliers();
4646
extern void add_the_blackbox_for_mults(FILE *out);
47-
extern void define_mult_function(nnode_t *node, short type, FILE *out);
47+
extern void define_mult_function(nnode_t *node, FILE *out);
4848
extern void split_multiplier(nnode_t *node, int a0, int b0, int a1, int b1);
4949
extern void iterate_multipliers(netlist_t *netlist);
5050
extern void clean_multipliers();

‎ODIN_II/SRC/include/simulate_blif.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ OTHER DEALINGS IN THE SOFTWARE.
6161
#define SINGLE_PORT_MEMORY_NAME "single_port_ram"
6262
#define DUAL_PORT_MEMORY_NAME "dual_port_ram"
6363

64+
#define DEFAULT_CLOCK_NAME "GLOBAL_SIM_BASE_CLK"
6465

6566
typedef struct {
6667
int number_of_pins;

‎ODIN_II/SRC/include/types.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -550,6 +550,9 @@ struct npin_t_t
550550

551551
signed char *values; // The values for the current wave.
552552
int *cycle; // The last cycle the pin was computed for.
553+
554+
bool delay_cycle;
555+
553556
unsigned long coverage;
554557
bool is_default; // The pin is feeding a mux from logic representing an else or default.
555558
bool is_implied; // This signal is implied.

‎ODIN_II/SRC/multipliers.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,7 @@ void add_the_blackbox_for_mults(FILE *out)
505505
/*-------------------------------------------------------------------------
506506
* (function: define_mult_function)
507507
*-----------------------------------------------------------------------*/
508-
void define_mult_function(nnode_t *node, short /*type*/, FILE *out)
508+
void define_mult_function(nnode_t *node, FILE *out)
509509
{
510510
int i, j;
511511
int count;

‎ODIN_II/SRC/output_blif.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,7 @@ short haveOutputLatchBlackbox = FALSE;
4646
void depth_first_traversal_to_output(short marker_value, FILE *fp, netlist_t *netlist);
4747
void depth_traverse_output_blif(nnode_t *node, int traverse_mark_number, FILE *fp);
4848
void output_node(nnode_t *node, short traverse_number, FILE *fp);
49-
void define_logical_function(nnode_t *node, short type, FILE *out);
49+
void define_logical_function(nnode_t *node, FILE *out);
5050
void define_set_input_logical_function(nnode_t *node, const char *bit_output, FILE *out);
5151
void define_ff(nnode_t *node, FILE *out);
5252
void define_decoded_mux(nnode_t *node, FILE *out);
@@ -341,7 +341,7 @@ void output_node(nnode_t *node, short /*traverse_number*/, FILE *fp)
341341
case LOGICAL_EQUAL:
342342
case NOT_EQUAL:
343343
case LOGICAL_NOT:
344-
define_logical_function(node, node->type, fp);
344+
define_logical_function(node, fp);
345345
break;
346346

347347
case MUX_2:
@@ -355,26 +355,26 @@ void output_node(nnode_t *node, short /*traverse_number*/, FILE *fp)
355355
case MULTIPLY:
356356
if (hard_multipliers == NULL)
357357
oassert(FALSE); /* should be soft logic! */
358-
define_mult_function(node, node->type, fp);
358+
define_mult_function(node, fp);
359359

360360
break;
361361

362362
//case FULLADDER:
363363
case ADD:
364364
if (hard_adders == NULL)
365365
oassert(FALSE); /* should be soft logic! */
366-
define_add_function(node, node->type, fp);
366+
define_add_function(node, fp);
367367
break;
368368

369369
case MINUS:
370370
oassert(hard_adders); /* should be soft logic! */
371371
if(hard_adders)
372-
define_add_function(node, node->type, fp);
372+
define_add_function(node, fp);
373373
break;
374374

375375
case MEMORY:
376376
case HARD_IP:
377-
define_hard_block(node, node->type, fp);
377+
define_hard_block(node, fp);
378378
break;
379379
case INPUT_NODE:
380380
case OUTPUT_NODE:
@@ -411,7 +411,7 @@ void output_node(nnode_t *node, short /*traverse_number*/, FILE *fp)
411411
/*-------------------------------------------------------------------------
412412
* (function: define_logical_function)
413413
*-----------------------------------------------------------------------*/
414-
void define_logical_function(nnode_t *node, short /*type*/, FILE *out)
414+
void define_logical_function(nnode_t *node, FILE *out)
415415
{
416416
int i, j;
417417
char *temp_string;

‎ODIN_II/SRC/partial_map.cpp

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -51,10 +51,10 @@ void instantiate_buffer(nnode_t *node, short mark, netlist_t *netlist);
5151
void instantiate_bitwise_logic(nnode_t *node, operation_list op, short mark, netlist_t *netlist);
5252
void instantiate_bitwise_reduction(nnode_t *node, operation_list op, short mark, netlist_t *netlist);
5353
void instantiate_logical_logic(nnode_t *node, operation_list op, short mark, netlist_t *netlist);
54-
void instantiate_EQUAL(nnode_t *node, short type, short mark, netlist_t *netlist);
55-
void instantiate_GE(nnode_t *node, short type, short mark, netlist_t *netlist);
56-
void instantiate_GT(nnode_t *node, short type, short mark, netlist_t *netlist);
57-
void instantiate_shift_left_or_right(nnode_t *node, short type, short mark, netlist_t *netlist);
54+
void instantiate_EQUAL(nnode_t *node, operation_list type, short mark, netlist_t *netlist);
55+
void instantiate_GE(nnode_t *node, operation_list type, short mark, netlist_t *netlist);
56+
void instantiate_GT(nnode_t *node, operation_list type, short mark, netlist_t *netlist);
57+
void instantiate_shift_left_or_right(nnode_t *node, operation_list type, short mark, netlist_t *netlist);
5858
void instantiate_unary_sub(nnode_t *node, short mark, netlist_t *netlist);
5959
void instantiate_sub_w_carry(nnode_t *node, short mark, netlist_t *netlist);
6060

@@ -677,7 +677,7 @@ void instantiate_unary_sub(nnode_t *node, short mark, netlist_t *netlist)
677677
* Builds the hardware for an equal comparison by building EQ for parallel lines and then
678678
* taking them all through an AND tree.
679679
*-------------------------------------------------------------------------------------------*/
680-
void instantiate_EQUAL(nnode_t *node, short type, short mark, netlist_t *netlist)
680+
void instantiate_EQUAL(nnode_t *node, operation_list type, short mark, netlist_t *netlist)
681681
{
682682
int width_a;
683683
int width_b;
@@ -763,7 +763,7 @@ void instantiate_EQUAL(nnode_t *node, short type, short mark, netlist_t *netlist
763763
* Defines the HW needed for greter than equal with EQ, GT, AND and OR gates to create
764764
* the appropriate logic function.
765765
*-------------------------------------------------------------------------------------------*/
766-
void instantiate_GT(nnode_t *node, short type, short mark, netlist_t *netlist)
766+
void instantiate_GT(nnode_t *node, operation_list type, short mark, netlist_t *netlist)
767767
{
768768
int width_a;
769769
int width_b;
@@ -808,7 +808,8 @@ void instantiate_GT(nnode_t *node, short type, short mark, netlist_t *netlist)
808808
port_B_offset = 0;
809809
port_A_index = 0;
810810
port_B_index = 0;
811-
error_message(NETLIST_ERROR, node->related_ast_node->line_number, node->related_ast_node->file_number, "Invalid node type in instantiate_GT\n");
811+
error_message(NETLIST_ERROR, node->related_ast_node->line_number, node->related_ast_node->file_number, "Invalid node type %s in instantiate_GT\n",
812+
node_name_based_on_op(node));
812813
}
813814

814815
/* xor gate identifies if any bits don't match */
@@ -913,7 +914,7 @@ void instantiate_GT(nnode_t *node, short type, short mark, netlist_t *netlist)
913914
* Defines the HW needed for greter than equal with EQ, GT, AND and OR gates to create
914915
* the appropriate logic function.
915916
*-------------------------------------------------------------------------------------------*/
916-
void instantiate_GE(nnode_t *node, short type, short mark, netlist_t *netlist)
917+
void instantiate_GE(nnode_t *node, operation_list type, short mark, netlist_t *netlist)
917918
{
918919
int width_a;
919920
int width_b;
@@ -994,7 +995,7 @@ void instantiate_GE(nnode_t *node, short type, short mark, netlist_t *netlist)
994995
* (function: instantiate_shift_left_or_right )
995996
* Creates the hardware for a shift left or right operation by a constant size.
996997
*-------------------------------------------------------------------------------------------*/
997-
void instantiate_shift_left_or_right(nnode_t *node, short type, short mark, netlist_t *netlist)
998+
void instantiate_shift_left_or_right(nnode_t *node, operation_list type, short mark, netlist_t *netlist)
998999
{
9991000
/* these variables are used in an attempt so that I don't need if cases. Probably a bad idea, but fun */
10001001
int width;

‎ODIN_II/SRC/read_blif.cpp

Lines changed: 62 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,6 @@ int line_count;
5050
const char *BLIF_ONE_STRING = "ONE_VCC_CNS";
5151
const char *BLIF_ZERO_STRING = "ZERO_GND_ZERO";
5252
const char *BLIF_PAD_STRING = "ZERO_PAD_ZERO";
53-
const char *DEFAULT_CLOCK_NAME = "top^clock";
5453

5554
// Stores pin names of the form port[pin]
5655
typedef struct {
@@ -92,6 +91,7 @@ typedef struct {
9291

9392
netlist_t * blif_netlist;
9493
short static skip_reading_bit_map=FALSE;
94+
bool insert_global_clock;
9595

9696

9797
void rb_create_top_driver_nets(const char *instance_name_prefix, hashtable_t *output_nets_hash);
@@ -139,6 +139,7 @@ int count_blif_lines(FILE *file);
139139
*/
140140
netlist_t *read_blif()
141141
{
142+
insert_global_clock = true;
142143
current_parse_file = 0;
143144
blif_netlist = allocate_netlist();
144145
/*Opening the blif file */
@@ -355,7 +356,15 @@ void create_latch_node_and_driver(FILE *file, hashtable_t *output_nets_hash)
355356
}
356357
else
357358
{
358-
error_message(NETLIST_ERROR,current_parse_file,file_line_number, "This .latch Format not supported \n\t required format :.latch <input> <output> [<type> <control/clock>] <initial val>");
359+
std::string line = "";
360+
for(int i=0; i< input_token_count; i++)
361+
{
362+
line += names[i];
363+
line += " ";
364+
}
365+
366+
error_message(NETLIST_ERROR,current_parse_file,file_line_number, "This .latch Format not supported: <%s> \n\t required format :.latch <input> <output> [<type> <control/clock>] <initial val>",
367+
line.c_str());
359368
}
360369
}
361370

@@ -1028,53 +1037,71 @@ short read_bit_map_find_unknown_gate(int input_count, nnode_t *node, FILE *file)
10281037
* function: add_top_input_nodes
10291038
to add the top level inputs to the netlist
10301039
*-------------------------------------------------------------------------------------------*/
1031-
void add_top_input_nodes(FILE *file, hashtable_t *output_nets_hash)
1040+
static void build_top_input_node(const char *name_str, hashtable_t *output_nets_hash)
10321041
{
1033-
char *ptr;
1034-
char buffer[READ_BLIF_BUFFER];
1035-
while ((ptr = vtr::strtok (NULL, TOKENS, file, buffer)))
1036-
{
1037-
char *temp_string = make_full_ref_name(ptr, NULL, NULL,NULL, -1);
1042+
char *temp_string = make_full_ref_name(name_str, NULL, NULL,NULL, -1);
10381043

1039-
/* create a new top input node and net*/
1044+
/* create a new top input node and net*/
10401045

1041-
nnode_t *new_node = allocate_nnode();
1046+
nnode_t *new_node = allocate_nnode();
10421047

1043-
new_node->related_ast_node = NULL;
1044-
new_node->type = INPUT_NODE;
1048+
new_node->related_ast_node = NULL;
1049+
new_node->type = INPUT_NODE;
10451050

1046-
/* add the name of the input variable */
1047-
new_node->name = temp_string;
1051+
/* add the name of the input variable */
1052+
new_node->name = temp_string;
10481053

1049-
/* allocate the pins needed */
1050-
allocate_more_output_pins(new_node, 1);
1051-
add_output_port_information(new_node, 1);
1054+
new_node->file_number = current_parse_file;
1055+
new_node->line_number = line_count;
10521056

1053-
/* Create the pin connection for the net */
1054-
npin_t *new_pin = allocate_npin();
1055-
new_pin->name = vtr::strdup(temp_string);
1056-
new_pin->type = OUTPUT;
1057+
/* allocate the pins needed */
1058+
allocate_more_output_pins(new_node, 1);
1059+
add_output_port_information(new_node, 1);
10571060

1058-
/* hookup the pin, net, and node */
1059-
add_output_pin_to_node(new_node, new_pin, 0);
1061+
/* Create the pin connection for the net */
1062+
npin_t *new_pin = allocate_npin();
1063+
new_pin->name = vtr::strdup(temp_string);
1064+
new_pin->type = OUTPUT;
10601065

1061-
nnet_t *new_net = allocate_nnet();
1062-
new_net->name = vtr::strdup(temp_string);
1066+
/* hookup the pin, net, and node */
1067+
add_output_pin_to_node(new_node, new_pin, 0);
10631068

1064-
add_driver_pin_to_net(new_net, new_pin);
1069+
nnet_t *new_net = allocate_nnet();
1070+
new_net->name = vtr::strdup(temp_string);
10651071

1066-
blif_netlist->top_input_nodes = (nnode_t**)vtr::realloc(blif_netlist->top_input_nodes, sizeof(nnode_t*)*(blif_netlist->num_top_input_nodes+1));
1067-
blif_netlist->top_input_nodes[blif_netlist->num_top_input_nodes++] = new_node;
1068-
new_node->file_number = current_parse_file;
1069-
new_node->line_number = line_count;
1072+
add_driver_pin_to_net(new_net, new_pin);
1073+
1074+
blif_netlist->top_input_nodes = (nnode_t**)vtr::realloc(blif_netlist->top_input_nodes, sizeof(nnode_t*)*(blif_netlist->num_top_input_nodes+1));
1075+
blif_netlist->top_input_nodes[blif_netlist->num_top_input_nodes++] = new_node;
10701076

1071-
//long sc_spot = sc_add_string(output_nets_sc, temp_string);
1072-
//if (output_nets_sc->data[sc_spot])
1073-
//warning_message(NETLIST_ERROR,linenum,-1, "Net (%s) with the same name already created\n",temp_string);
1077+
//long sc_spot = sc_add_string(output_nets_sc, temp_string);
1078+
//if (output_nets_sc->data[sc_spot])
1079+
//warning_message(NETLIST_ERROR,linenum,-1, "Net (%s) with the same name already created\n",temp_string);
10741080

1075-
//output_nets_sc->data[sc_spot] = new_net;
1081+
//output_nets_sc->data[sc_spot] = new_net;
10761082

1077-
output_nets_hash->add(output_nets_hash, temp_string, strlen(temp_string)*sizeof(char), new_net);
1083+
output_nets_hash->add(output_nets_hash, temp_string, strlen(temp_string)*sizeof(char), new_net);
1084+
}
1085+
1086+
void add_top_input_nodes(FILE *file, hashtable_t *output_nets_hash)
1087+
{
1088+
/**
1089+
* insert a global clock for fall back.
1090+
* in case of undriven internal clocks, they will attach to the global clock
1091+
* this also fix the issue of constant verilog (no input)
1092+
* that cannot simulate due to empty input vector
1093+
*/
1094+
if(insert_global_clock)
1095+
{
1096+
insert_global_clock = false;
1097+
build_top_input_node(DEFAULT_CLOCK_NAME, output_nets_hash);
1098+
}
1099+
1100+
char *ptr;
1101+
char buffer[READ_BLIF_BUFFER];
1102+
while ((ptr = vtr::strtok (NULL, TOKENS, file, buffer)))
1103+
{
1104+
build_top_input_node(ptr, output_nets_hash);
10781105
}
10791106
}
10801107

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