fix memory padding on soft memory

Author: jeanlego

ODIN_II/SRC/hard_blocks.cpp

@@ -169,10 +169,13 @@ void define_hard_block(nnode_t *node, short /*type*/, FILE *out)
 	for (i = 0;  i < node->num_input_pins; i++)
 	{
 		/* Check that the input pin is driven */
-		if (node->input_pins[i]->net->driver_pin == NULL)
+		if (node->input_pins[i]->net->driver_pin == NULL
+		&& node->input_pins[i]->net != verilog_netlist->zero_net
+		&& node->input_pins[i]->net != verilog_netlist->one_net
+		&& node->input_pins[i]->net != verilog_netlist->pad_net)
 		{
-			printf("Signal %s is not driven. Odin will terminate.\n", node->input_pins[i]->name);
-			exit(1);
+			warning_message(NETLIST_ERROR, -1, -1, "Signal %s is not driven. padding with ground\n", node->input_pins[i]->name);
+			add_fanout_pin_to_net(verilog_netlist->zero_net, node->input_pins[i]);
 		}
 
 		if (node->input_port_sizes[port] == 1)

ODIN_II/SRC/include/odin_ii.h

@@ -2,7 +2,7 @@
 #define ODIN_II_H
 
 struct netlist_t_t *start_odin_ii(int argc,char **argv);
-int terminate_odin_ii();
+int terminate_odin_ii(struct netlist_t_t *odin_netlist);
 
 void set_default_config();
 void get_options(int argc, char **argv);

ODIN_II/SRC/include/read_blif.h

@@ -1,7 +1,7 @@
 #ifndef READ_BLIF_H
 #define READ_BLIF_H
 
-void read_blif();
+netlist_t *read_blif();
 extern int line_count;
 
 #endif

ODIN_II/SRC/include/types.h

@@ -149,6 +149,8 @@ typedef enum {
 /* the global arguments of the software */
 struct global_args_t_t
 {
+	std::string program_name;
+
     argparse::ArgValue<char*> config_file;
 	argparse::ArgValue<std::vector<std::string>> verilog_files;
 	argparse::ArgValue<char*> blif_file;

ODIN_II/SRC/memories.cpp

@@ -1467,6 +1467,13 @@ void instantiate_soft_single_port_ram(nnode_t *node, short mark, netlist_t *netl
 	for (i = 0; i < num_addr; i++)
 	{
 		npin_t *address_pin = decoder->pins[i];
+		/* Check that the input pin is driven */
+		oassert(
+			address_pin->net->driver_pin != NULL
+			|| address_pin->net == verilog_netlist->zero_net
+			|| address_pin->net == verilog_netlist->one_net
+			|| address_pin->net == verilog_netlist->pad_net
+		);
 
 		// An AND gate to enable and disable writing.
 		nnode_t *and_g = make_1port_logic_gate(LOGICAL_AND, 2, node, mark);
@@ -1490,6 +1497,13 @@ void instantiate_soft_single_port_ram(nnode_t *node, short mark, netlist_t *netl
 		for (j = 0; j < num_addr; j++)
 		{
 			npin_t *address_pin = decoder->pins[j];
+			/* Check that the input pin is driven */
+			oassert(
+				address_pin->net->driver_pin != NULL
+				|| address_pin->net == verilog_netlist->zero_net
+				|| address_pin->net == verilog_netlist->one_net
+				|| address_pin->net == verilog_netlist->pad_net
+			);
 
 			// A multiplexer switches between accepting incoming data and keeping existing data.
 			nnode_t *mux = make_2port_gate(MUX_2, 2, 2, 1, node, mark);
@@ -1566,6 +1580,19 @@ void instantiate_soft_dual_port_ram(nnode_t *node, short mark, netlist_t *netlis
 		npin_t *addr1_pin = decoder1->pins[i];
 		npin_t *addr2_pin = decoder2->pins[i];
 
+		oassert(
+			addr1_pin->net->driver_pin != NULL
+			|| addr1_pin->net == verilog_netlist->zero_net
+			|| addr1_pin->net == verilog_netlist->one_net
+			|| addr1_pin->net == verilog_netlist->pad_net
+		);
+		oassert(
+			addr2_pin->net->driver_pin != NULL
+			|| addr2_pin->net == verilog_netlist->zero_net
+			|| addr2_pin->net == verilog_netlist->one_net
+			|| addr2_pin->net == verilog_netlist->pad_net
+		);
+
 		// Write enable and gate for address 1.
 		nnode_t *and1 = make_1port_logic_gate(LOGICAL_AND, 2, node, mark);
 		add_input_pin_to_node(and1, addr1_pin, 0);
@@ -1606,6 +1633,19 @@ void instantiate_soft_dual_port_ram(nnode_t *node, short mark, netlist_t *netlis
 			npin_t *addr1_pin = decoder1->pins[j];
 			npin_t *addr2_pin = decoder2->pins[j];
 
+		oassert(
+			addr1_pin->net->driver_pin != NULL
+			|| addr1_pin->net == verilog_netlist->zero_net
+			|| addr1_pin->net == verilog_netlist->one_net
+			|| addr1_pin->net == verilog_netlist->pad_net
+		);
+		oassert(
+			addr2_pin->net->driver_pin != NULL
+			|| addr2_pin->net == verilog_netlist->zero_net
+			|| addr2_pin->net == verilog_netlist->one_net
+			|| addr2_pin->net == verilog_netlist->pad_net
+		);
+
 			// The data mux selects between the two data lines for this address.
 			nnode_t *data_mux = make_2port_gate(MUX_2, 2, 2, 1, node, mark);
 			// Port 2 before 1 to mimic the simulator's behaviour when the addresses are the same.
@@ -1686,6 +1726,15 @@ signal_list_t *create_decoder(nnode_t *node, short mark, signal_list_t *input_li
 	int i;
 	for (i = 0; i < num_inputs; i++)
 	{
+		if(input_list->pins[i]->net->driver_pin == NULL
+		&& input_list->pins[i]->net != verilog_netlist->zero_net
+		&& input_list->pins[i]->net != verilog_netlist->one_net
+		&& input_list->pins[i]->net != verilog_netlist->pad_net)
+		{
+			warning_message(NETLIST_ERROR, -1, -1, "Signal %s is not driven. padding with ground\n", input_list->pins[i]);
+			add_fanout_pin_to_net(verilog_netlist->zero_net, input_list->pins[i]);
+		}
+
 		nnode_t *not_g = make_not_gate(node, mark);
 		remap_pin_to_new_node(input_list->pins[i], not_g, 0);
 		npin_t *not_output = allocate_npin();

ODIN_II/SRC/netlist_utils.cpp

@@ -895,6 +895,9 @@ netlist_t* allocate_netlist()
  *-------------------------------------------------------------------------------------------*/
 void free_netlist(netlist_t *to_free)
 {
+	if(!to_free)
+		return;
+		
 	sc_free_string_cache(to_free->nets_sc);
 	sc_free_string_cache(to_free->out_pins_sc);
 	sc_free_string_cache(to_free->nodes_sc);