ci stuck #2

Author: poname

.github/workflows/test.yml

@@ -34,7 +34,7 @@ jobs:
           # - {test: "vtr_reg_nightly_test6", cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON",                           extra_pkgs: ""}
           # - {test: "vtr_reg_strong",        cores: "16", options: "",          cmake: "-DVTR_ASSERT_LEVEL=3",                          extra_pkgs: "libeigen3-dev"}
           # - {test: "vtr_reg_strong",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON", extra_pkgs: "libeigen3-dev"}
-          # - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON",     extra_pkgs: ""}
+          - {test: "vtr_reg_yosys",         cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON",     extra_pkgs: ""}
           - {test: "vtr_reg_yosys_parmys",  cores: "16", options: "",          cmake: "-DWITH_YOSYS=ON -DYOSYS_PARMYS_PLUGIN=ON",      extra_pkgs: ""}
           # - {test: "vtr_reg_yosys_odin",    cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON -DYOSYS_SV_UHDM_PLUGIN=ON", extra_pkgs: ""}
           # - {test: "odin_tech_strong",      cores: "16", options: "",          cmake: "-DODIN_USE_YOSYS=ON",                           extra_pkgs: ""}

vtr_flow/tasks/regression_tests/vtr_reg_yosys/task_list.txt

@@ -1,7 +1,7 @@
-regression_tests/vtr_reg_yosys/f4pga_button_controller/
-regression_tests/vtr_reg_yosys/f4pga_pulse_width_led/
-regression_tests/vtr_reg_yosys/f4pga_timer/
+#regression_tests/vtr_reg_yosys/f4pga_button_controller/
+#regression_tests/vtr_reg_yosys/f4pga_pulse_width_led/
+#regression_tests/vtr_reg_yosys/f4pga_timer/
 regression_tests/vtr_reg_yosys/vtr_benchmarks/
 #regression_tests/vtr_reg_yosys/vexriscv/
-regression_tests/vtr_reg_yosys/ultraembedded/
-regression_tests/vtr_reg_yosys/freecores/
+#regression_tests/vtr_reg_yosys/ultraembedded/
+#regression_tests/vtr_reg_yosys/freecores/

vtr_flow/tasks/regression_tests/vtr_reg_yosys/vtr_benchmarks/config/config.txt

@@ -26,11 +26,11 @@ circuit_list_add=sha.v
 circuit_list_add=spree.v
 circuit_list_add=stereovision0.v
 circuit_list_add=stereovision1.v
-circuit_list_add=stereovision2.v
+#circuit_list_add=stereovision2.v
 circuit_list_add=stereovision3.v
-circuit_list_add=LU8PEEng.v
-circuit_list_add=LU32PEEng.v
-circuit_list_add=mcml.v
+#circuit_list_add=LU8PEEng.v
+#circuit_list_add=LU32PEEng.v
+#circuit_list_add=mcml.v
 
 # Add architectures to list to sweep
 arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml

vtr_flow/tasks/regression_tests/vtr_reg_yosys_parmys/task_list.txt

@@ -1,9 +1,9 @@
 regression_tests/vtr_reg_yosys_parmys/vtr_benchmarks/
-regression_tests/vtr_reg_yosys_parmys/koios/
-regression_tests/vtr_reg_yosys_parmys/ultraembedded/
-regression_tests/vtr_reg_yosys_parmys/vexriscv/
-regression_tests/vtr_reg_yosys_parmys/freecores/
+#regression_tests/vtr_reg_yosys_parmys/koios/
+#regression_tests/vtr_reg_yosys_parmys/ultraembedded/
+#regression_tests/vtr_reg_yosys_parmys/vexriscv/
+#regression_tests/vtr_reg_yosys_parmys/freecores/
 #regression_tests/vtr_reg_yosys_parmys/system_verilog/f4pga_button_controller/
 #regression_tests/vtr_reg_yosys_parmys/system_verilog/f4pga_pulse_width_led/
 #regression_tests/vtr_reg_yosys_parmys/system_verilog/f4pga_timer/
-regression_tests/vtr_reg_yosys_parmys/mips32r1/
+#regression_tests/vtr_reg_yosys_parmys/mips32r1/