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[Infra]: - fix SPRAM/DPRAM VPR packing issue for circuits synthesized by Yosys
 - fix a concatenation bug in arm_core caused failure in ABC for circuits synthesized by Yosys - remove SPRAM/DPRAM rename files - add info to Yosys synthesis script Signed-off-by: Seyed Alireza Damghani <[email protected]>
1 parent 09c2a9f commit ccc7ea8

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9 files changed

+27
-289
lines changed

9 files changed

+27
-289
lines changed

‎vtr_flow/benchmarks/verilog/arm_core.v

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4048,7 +4048,7 @@ reg [31:0] r11 = 32'hdeadbeef;
40484048
reg [31:0] r12 = 32'hdeadbeef;
40494049
reg [31:0] r13 = 32'hdeadbeef;
40504050
reg [31:0] r14 = 32'hdeadbeef;
4051-
reg [23:0] r15 = 24'hc0ffee;
4051+
reg [23:0] r15; // line: 4272
40524052

40534053
wire [31:0] r0_out;
40544054
wire [31:0] r1_out;
@@ -4268,7 +4268,8 @@ assign r15_out_rm_nxt = { i_status_bits_flags,
42684268
i_status_bits_firq_mask,
42694269
i_pc,
42704270
i_mode_exec};
4271-
4271+
4272+
// if r15 is initialized => Yosys+ABC:A CI/CO pair share the name (u_execute.u_register_bank.r15[1]) but do not link directly
42724273
assign r15_out_rn = {6'd0, r15, 2'd0};
42734274

42744275

‎vtr_flow/misc/synthesis.ys

Lines changed: 15 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,17 @@
1-
# XXX is replaced with filename by the run_vtr_flow script
1+
#################################################################
2+
# Yosys synthesis script, including generic 'synth' commands, #
3+
# in addition to techmap asynchronous FFs and VTR hard blocks. #
4+
# Once the VTR flow runs with Yosys front-end, Yosys synthesize #
5+
# the input design using the following commands. #
6+
# #
7+
# NOTE: the script is adapted from the one Eddie Hung proposed #
8+
# for VTR-to-Bitstream[1]. However, a few minor changes to make #
9+
# it adaptable with the current VTR flow have been made. #
10+
# #
11+
# [1] http://eddiehung.github.io/vtb.html #
12+
#################################################################
13+
14+
# XXX (input circuit) is replaced with filename by the run_vtr_flow script
215
read_verilog -nolatches XXX
316

417
# These commands follow the generic `synth'
@@ -59,12 +72,6 @@ read_verilog -lib TTT/multiply.v
5972
read_verilog -lib SSS #(SSS) will be replaced by single_port_ram.v by python script
6073
read_verilog -lib DDD #(DDD) will be replaced by dual_port_ram.v by python script
6174

62-
# Rename singlePortRam to single_port_ram
63-
# Rename dualPortRam to dualZ_port_ram
64-
# rename function of Yosys not work here
65-
# since it may outcome hierarchy error
66-
read_verilog SSR #(SSR) will be replaced by spram_rename.v by python script
67-
read_verilog DDR #(DDR) will be replaced by dpram_rename.v by python script
6875

6976
flatten
7077
# Lastly, check the hierarchy for any unknown modules,
@@ -78,4 +85,4 @@ tee -o /dev/stdout stat
7885
# the internal `$true'/`$false' signals vcc/gnd, but
7986
# switch `-impltf' doesn't output them
8087
# ZZZ will be replaced by run_vtr_flow.pl
81-
write_blif -true - vcc -false - gnd -undef - unconn -blackbox ZZZ
88+
write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ

‎vtr_flow/misc/yosyslib/dpram_rename.v

Lines changed: 0 additions & 60 deletions
This file was deleted.

‎vtr_flow/misc/yosyslib/dual_port_ram.v

Lines changed: 4 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -3,97 +3,17 @@
33
`define MEM_MAXADDR PPP
44
`define MEM_MAXDATA 36
55

6-
// depth and data may need to be splited
7-
module dual_port_ram(clk, we1, we2, addr1, addr2, data1, data2, out1, out2);
8-
parameter ADDR_WIDTH = 1;
6+
module dual_port_ram(clk, data2, data1, addr2, addr1, we2, we1, out2, out1);
7+
parameter ADDR_WIDTH = `MEM_MAXADDR;
98
parameter DATA_WIDTH = 1;
109

11-
input clk;
12-
input we1, we2;
13-
input [ADDR_WIDTH-1:0] addr1, addr2;
14-
input [DATA_WIDTH-1:0] data1, data2;
15-
16-
output reg [DATA_WIDTH-1:0] out1, out2;
17-
18-
genvar i;
19-
generate
20-
// split in depth
21-
if (ADDR_WIDTH > `MEM_MAXADDR)
22-
begin
23-
24-
wire [ADDR_WIDTH-2:0] new_addr1 = addr1[ADDR_WIDTH-2:0];
25-
wire [ADDR_WIDTH-2:0] new_addr2 = addr2[ADDR_WIDTH-2:0];
26-
27-
wire [DATA_WIDTH-1:0] out1_h, out1_l;
28-
wire [DATA_WIDTH-1:0] out2_h, out2_l;
29-
30-
31-
defparam uut_h.ADDR_WIDTH = ADDR_WIDTH-1;
32-
defparam uut_h.DATA_WIDTH = DATA_WIDTH;
33-
dual_port_ram uut_h (
34-
.clk(clk),
35-
.we1(we1),
36-
.we2(we2),
37-
.addr1(new_addr1),
38-
.addr2(new_addr2),
39-
.data1(data1),
40-
.data2(data2),
41-
.out1(out1_h),
42-
.out2(out2_h)
43-
);
44-
45-
defparam uut_l.ADDR_WIDTH = ADDR_WIDTH-1;
46-
defparam uut_l.DATA_WIDTH = DATA_WIDTH;
47-
dual_port_ram uut_l (
48-
.clk(clk),
49-
.we1(we1),
50-
.we2(we2),
51-
.addr1(new_addr1),
52-
.addr2(new_addr2),
53-
.data1(data1),
54-
.data2(data2),
55-
.out1(out1_l),
56-
.out2(out2_l)
57-
);
58-
59-
reg additional_bit;
60-
always @(posedge clk) additional_bit <= addr[ADDR_WIDTH-1];
61-
assign out1 = (additional_bit) ? out1_h : out1_l;
62-
assign out2 = (additional_bit) ? out2_h : out2_l;
63-
64-
end else begin
65-
for (i = 0; i < DATA_WIDTH; i = i + 1) begin:single_bit_data
66-
dualPortRam uut (
67-
.clk(clk),
68-
.we1(we1),
69-
.we2(we2),
70-
.addr1(addr1),
71-
.addr2(addr2),
72-
.data1(data1[i]),
73-
.data2(data2[i]),
74-
.out1(out1[i]),
75-
.out2(out2[i])
76-
);
77-
end
78-
end
79-
endgenerate
80-
81-
endmodule
82-
83-
84-
85-
(* blackbox *)
86-
module dualPortRam(clk, data2, data1, addr2, addr1, we2, we1, out2, out1);
87-
localparam ADDR_WIDTH = `MEM_MAXADDR;
88-
localparam DATA_WIDTH = 1;
89-
9010
input clk;
9111
input we1, we2;
9212
input [ADDR_WIDTH-1:0] addr1, addr2;
9313
input data1, data2;
9414

9515
output reg out1, out2;
96-
/*
16+
9717
reg [DATA_WIDTH-1:0] RAM [(1<<ADDR_WIDTH)-1:0];
9818

9919
always @(posedge clk)
@@ -106,5 +26,5 @@ module dualPortRam(clk, data2, data1, addr2, addr1, we2, we1, out2, out1);
10626
out1 <= RAM[addr1];
10727
out2 <= RAM[addr2];
10828
end
109-
*/
29+
11030
endmodule

‎vtr_flow/misc/yosyslib/single_port_ram.v

Lines changed: 4 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -3,81 +3,18 @@
33
`define MEM_MAXADDR PPP
44
`define MEM_MAXDATA 36
55

6-
// depth and data may need to be splited
7-
module single_port_ram(clk, we, addr, data, out);
6+
module single_port_ram(clk, data, addr, we, out);
87

9-
parameter ADDR_WIDTH = 1;
8+
parameter ADDR_WIDTH = `MEM_MAXADDR;
109
parameter DATA_WIDTH = 1;
1110

12-
input clk;
13-
input we;
14-
input [ADDR_WIDTH - 1:0] addr;
15-
input [DATA_WIDTH - 1:0] data;
16-
17-
output reg [DATA_WIDTH - 1:0] out;
18-
19-
genvar i;
20-
generate
21-
// split in depth
22-
if (ADDR_WIDTH > `MEM_MAXADDR)
23-
begin
24-
25-
wire [ADDR_WIDTH-2:0] new_addr = addr[ADDR_WIDTH-2:0];
26-
wire [DATA_WIDTH-1:0] out_h, out_l;
27-
28-
29-
defparam uut_h.ADDR_WIDTH = ADDR_WIDTH-1;
30-
defparam uut_h.DATA_WIDTH = DATA_WIDTH;
31-
single_port_ram uut_h (
32-
.clk(clk),
33-
.we(we),
34-
.addr(new_addr),
35-
.data(data),
36-
.out(out_h)
37-
);
38-
39-
defparam uut_l.ADDR_WIDTH = ADDR_WIDTH-1;
40-
defparam uut_l.DATA_WIDTH = DATA_WIDTH;
41-
single_port_ram uut_l (
42-
.clk(clk),
43-
.we(we),
44-
.addr(new_addr),
45-
.data(data),
46-
.out(out_l)
47-
);
48-
49-
reg additional_bit;
50-
always @(posedge clk) additional_bit <= addr[ADDR_WIDTH-1];
51-
assign out = (additional_bit) ? out_h : out_l;
52-
53-
end else begin
54-
for (i = 0; i < DATA_WIDTH; i = i + 1) begin:single_bit_data
55-
singlePortRam uut (
56-
.clk(clk),
57-
.we(we),
58-
.addr(addr),
59-
.data(data[i]),
60-
.out(out[i])
61-
);
62-
end
63-
end
64-
endgenerate
65-
66-
endmodule
67-
68-
(* blackbox *)
69-
module singlePortRam(clk, data, addr, we, out);
70-
71-
localparam ADDR_WIDTH = `MEM_MAXADDR;
72-
localparam DATA_WIDTH = 1;
73-
7411
input clk;
7512
input we;
7613
input [ADDR_WIDTH-1:0] addr;
7714
input [DATA_WIDTH-1:0] data;
7815

7916
output reg [DATA_WIDTH-1:0] out;
80-
/*
17+
8118
reg [DATA_WIDTH-1:0] RAM [(1<<ADDR_WIDTH)-1:0];
8219

8320
always @(posedge clk)
@@ -87,5 +24,5 @@ module singlePortRam(clk, data, addr, we, out);
8724

8825
out <= RAM[addr];
8926
end
90-
*/
27+
9128
endmodule

‎vtr_flow/misc/yosyslib/spram_rename.v

Lines changed: 0 additions & 49 deletions
This file was deleted.

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