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sdamghansdamghan
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[Infra]: - fix \$mem missed RD_EN port in yosys models
 - fail techmap if read enable is constant low - retrieve arm_core implicit memory Signed-off-by: Seyed Alireza Damghani <[email protected]>
1 parent 91cf6ad commit 09c2a9f

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2 files changed

+51
-35
lines changed

2 files changed

+51
-35
lines changed

‎vtr_flow/benchmarks/verilog/arm_core.v

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -21,15 +21,14 @@ module single_port_ram_21_8(
2121

2222
reg [`DATA_WIDTH_21_8-1:0] RAM[255:0];
2323

24-
defparam sram_replace_21_8.ADDR_WIDTH = `ADDR_WIDTH_21_8;
25-
defparam sram_replace_21_8.DATA_WIDTH = `DATA_WIDTH_21_8;
26-
single_port_ram sram_replace_21_8 (
27-
.clk (clk),
28-
.addr (addr),
29-
.data (data),
30-
.we (we),
31-
.out (out)
32-
);
24+
always @ (posedge clk)
25+
begin
26+
if (we)
27+
begin
28+
RAM[addr] <= data;
29+
out <= RAM[addr];
30+
end
31+
end
3332

3433
endmodule
3534

@@ -56,15 +55,14 @@ module single_port_ram_128_8(
5655

5756
reg [`DATA_WIDTH_128_8-1:0] RAM[255:0];
5857

59-
defparam sram_replace_128_8.ADDR_WIDTH = `ADDR_WIDTH_128_8;
60-
defparam sram_replace_128_8.DATA_WIDTH = `DATA_WIDTH_128_8;
61-
single_port_ram sram_replace_128_8 (
62-
.clk (clk),
63-
.addr (addr),
64-
.data (data),
65-
.we (we),
66-
.out (out)
67-
);
58+
always @ (posedge clk)
59+
begin
60+
if (we)
61+
begin
62+
RAM[addr] <= data;
63+
out <= RAM[addr];
64+
end
65+
end
6866

6967
endmodule
7068

‎vtr_flow/misc/yosyslib/yosys_models.v

Lines changed: 35 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -11,38 +11,44 @@
1111
`define MAX(a,b) (a > b ? a : b)
1212
`define MIN(a,b) (a < b ? a : b)
1313

14-
module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
14+
module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
1515
parameter MEMID = "";
1616
parameter SIZE = 256;
1717
parameter OFFSET = 0;
1818
parameter ABITS = 8;
1919
parameter WIDTH = 8;
20-
parameter INIT = 0;
21-
20+
parameter signed INIT = 1'bx;
21+
2222
parameter RD_PORTS = 1;
2323
parameter RD_CLK_ENABLE = 1'b1;
2424
parameter RD_CLK_POLARITY = 1'b1;
2525
parameter RD_TRANSPARENT = 1'b1;
26-
26+
2727
parameter WR_PORTS = 1;
2828
parameter WR_CLK_ENABLE = 1'b1;
2929
parameter WR_CLK_POLARITY = 1'b1;
30-
30+
3131
input [RD_PORTS-1:0] RD_CLK;
32+
input [RD_PORTS-1:0] RD_EN;
3233
input [RD_PORTS*ABITS-1:0] RD_ADDR;
3334
output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
34-
35+
3536
input [WR_PORTS-1:0] WR_CLK;
37+
input [WR_PORTS*WIDTH-1:0] WR_EN;
3638
input [WR_PORTS*ABITS-1:0] WR_ADDR;
37-
input [WR_PORTS*WIDTH-1:0] WR_DATA, WR_EN;
38-
39+
input [WR_PORTS*WIDTH-1:0] WR_DATA;
40+
3941
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
4042

4143
parameter _TECHMAP_CONNMAP_RD_CLK_ = 0;
4244
parameter _TECHMAP_CONNMAP_WR_CLK_ = 0;
45+
4346
parameter _TECHMAP_CONNMAP_RD_ADDR_ = 0;
4447
parameter _TECHMAP_CONNMAP_WR_ADDR_ = 0;
48+
4549
parameter _TECHMAP_CONNMAP_WR_EN_ = 0;
50+
parameter _TECHMAP_CONSTVAL_RD_EN_ = 0;
51+
4652
parameter _TECHMAP_BITS_CONNMAP_ = 0;
4753
//parameter _TECHMAP_CONNMAP_RD_PORTS_ = 0;
4854
//parameter _TECHMAP_CONNMAP_WR_PORTS_ = 0;
@@ -55,6 +61,10 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
5561
if (RD_PORTS > 2 || WR_PORTS > 2)
5662
_TECHMAP_FAIL_ <= 1;
5763

64+
// read enable must not be constant low
65+
if (_TECHMAP_CONSTVAL_RD_EN_[0] == 1'b0)
66+
_TECHMAP_FAIL_ <= 1;
67+
5868
// we expect positive read clock and non-transparent reads
5969
if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY)
6070
_TECHMAP_FAIL_ <= 1;
@@ -78,16 +88,18 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
7888
initial begin
7989
// check each pair of read and write port are the same
8090
if (RD_PORTS >= i && WR_PORTS >= i) begin
81-
if (_TECHMAP_CONNMAP_RD_ADDR_[ABITS*_TECHMAP_BITS_CONNMAP_*(i+1)-1:ABITS*_TECHMAP_BITS_CONNMAP_*i] != _TECHMAP_CONNMAP_WR_ADDR_[ABITS*_TECHMAP_BITS_CONNMAP_*(i+1)-1:ABITS*_TECHMAP_BITS_CONNMAP_*i])
82-
_TECHMAP_FAIL_ <= 1;
91+
if (_TECHMAP_CONNMAP_RD_ADDR_[i*ABITS*_TECHMAP_BITS_CONNMAP_ +: ABITS*_TECHMAP_BITS_CONNMAP_] !=
92+
_TECHMAP_CONNMAP_WR_ADDR_[i*ABITS*_TECHMAP_BITS_CONNMAP_ +: ABITS*_TECHMAP_BITS_CONNMAP_])
93+
_TECHMAP_FAIL_ <= 1;
8394
end
8495
end
8596
// check all bits of write enable are the same
8697
if (i < WR_PORTS) begin
8798
genvar j;
8899
for (j = 1; j < WIDTH; j = j+1) begin
89100
initial begin
90-
if (_TECHMAP_CONNMAP_WR_EN_[(WIDTH*i+j+1)*_TECHMAP_BITS_CONNMAP_-1:(WIDTH*i+j)*_TECHMAP_BITS_CONNMAP_] != _TECHMAP_CONNMAP_WR_EN_[(WIDTH*i+1)*_TECHMAP_BITS_CONNMAP_-1:(WIDTH*i)*_TECHMAP_BITS_CONNMAP_])
101+
if (_TECHMAP_CONNMAP_WR_EN_[0 +: _TECHMAP_BITS_CONNMAP_] !=
102+
_TECHMAP_CONNMAP_WR_EN_[j*_TECHMAP_BITS_CONNMAP_ +: _TECHMAP_BITS_CONNMAP_])
91103
_TECHMAP_FAIL_ <= 1;
92104
end
93105
end
@@ -101,6 +113,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
101113
.WR_PORTS(WR_PORTS), .WR_CLK_ENABLE(WR_CLK_ENABLE), .WR_CLK_POLARITY(WR_CLK_POLARITY)
102114
) _TECHMAP_REPLACE_ (
103115
.RD_CLK(RD_CLK),
116+
.RD_EN(RD_EN),
104117
.RD_ADDR(RD_ADDR),
105118
.RD_DATA(RD_DATA),
106119
.WR_CLK(WR_CLK),
@@ -110,29 +123,32 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
110123
);
111124
endmodule
112125

113-
module \$__mem_gen (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
126+
module \$__mem_gen (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
114127
parameter MEMID = "";
115128
parameter SIZE = 256;
116129
parameter OFFSET = 0;
117130
parameter ABITS = 8;
118131
parameter WIDTH = 8;
119-
132+
parameter signed INIT = 1'bx;
133+
120134
parameter RD_PORTS = 1;
121135
parameter RD_CLK_ENABLE = 1'b1;
122136
parameter RD_CLK_POLARITY = 1'b1;
123137
parameter RD_TRANSPARENT = 1'b1;
124-
138+
125139
parameter WR_PORTS = 1;
126140
parameter WR_CLK_ENABLE = 1'b1;
127141
parameter WR_CLK_POLARITY = 1'b1;
128-
142+
129143
input [RD_PORTS-1:0] RD_CLK;
144+
input [RD_PORTS-1:0] RD_EN;
130145
input [RD_PORTS*ABITS-1:0] RD_ADDR;
131146
output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
132-
147+
133148
input [WR_PORTS-1:0] WR_CLK;
149+
input [WR_PORTS*WIDTH-1:0] WR_EN;
134150
input [WR_PORTS*ABITS-1:0] WR_ADDR;
135-
input [WR_PORTS*WIDTH-1:0] WR_DATA, WR_EN;
151+
input [WR_PORTS*WIDTH-1:0] WR_DATA;
136152

137153
wire [1023:0] _TECHMAP_DO_ = "proc; clean";
138154

@@ -158,6 +174,7 @@ module \$__mem_gen (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
158174
.WR_PORTS(WR_PORTS), .WR_CLK_ENABLE(WR_CLK_ENABLE), .WR_CLK_POLARITY(WR_CLK_POLARITY)
159175
) mem_hi (
160176
.RD_CLK(RD_CLK),
177+
.RD_EN(RD_EN),
161178
.RD_ADDR(rd_addr_new),
162179
.RD_DATA(rd_data_hi),
163180
.WR_CLK(WR_CLK),
@@ -176,6 +193,7 @@ module \$__mem_gen (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
176193
.WR_PORTS(WR_PORTS), .WR_CLK_ENABLE(WR_CLK_ENABLE), .WR_CLK_POLARITY(WR_CLK_POLARITY)
177194
) mem_lo (
178195
.RD_CLK(RD_CLK),
196+
.RD_EN(RD_EN),
179197
.RD_ADDR(rd_addr_new),
180198
.RD_DATA(rd_data_lo),
181199
.WR_CLK(WR_CLK),

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