@@ -887,11 +887,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
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}
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private: // Internal Helper functions
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- // /@brief Writes out the verilog netlist
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- void print_verilog (int depth = 0 ) {
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- verilog_os_ << indent (depth) << " //Verilog generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n " ;
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- verilog_os_ << indent (depth) << " module " << top_module_name_ << " (\n " ;
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-
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+ virtual void print_primary_io (int depth) {
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// Primary Inputs
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for (auto iter = inputs_.begin (); iter != inputs_.end (); ++iter) {
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verilog_os_ << indent (depth + 1 ) << " input " << escape_verilog_identifier (*iter);
@@ -900,7 +896,6 @@ class NetlistWriterVisitor : public NetlistVisitor {
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}
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verilog_os_ << " \n " ;
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}
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-
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// Primary Outputs
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for (auto iter = outputs_.begin (); iter != outputs_.end (); ++iter) {
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verilog_os_ << indent (depth + 1 ) << " output " << escape_verilog_identifier (*iter);
@@ -909,6 +904,22 @@ class NetlistWriterVisitor : public NetlistVisitor {
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}
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verilog_os_ << " \n " ;
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}
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+ }
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+
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+ virtual void print_assignments (int depth) {
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+ verilog_os_ << " \n " ;
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+ verilog_os_ << indent (depth + 1 ) << " //IO assignments\n " ;
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+ for (auto & assign : assignments_) {
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+ assign.print_verilog (verilog_os_, indent (depth + 1 ));
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+ }
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+ }
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+
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+ // /@brief Writes out the verilog netlist
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+ void print_verilog (int depth = 0 ) {
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+ verilog_os_ << indent (depth) << " //Verilog generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n " ;
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+ verilog_os_ << indent (depth) << " module " << top_module_name_ << " (\n " ;
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+
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+ print_primary_io (depth);
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verilog_os_ << indent (depth) << " );\n " ;
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// Wire declarations
@@ -924,11 +935,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
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}
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// connections between primary I/Os and their internal wires
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- verilog_os_ << " \n " ;
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- verilog_os_ << indent (depth + 1 ) << " //IO assignments\n " ;
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- for (auto & assign : assignments_) {
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- assign.print_verilog (verilog_os_, indent (depth + 1 ));
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- }
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+ print_assignments (depth);
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// Interconnect between cell instances
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verilog_os_ << " \n " ;
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