Skip to content

Commit bcd49bb

Browse files
committed
vpr: base: netlist writer: refactor verilog writer
Signed-off-by: Pawel Czarnecki <[email protected]>
1 parent cd8fb2b commit bcd49bb

File tree

1 file changed

+18
-11
lines changed

1 file changed

+18
-11
lines changed

vpr/src/base/netlist_writer.cpp

Lines changed: 18 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -887,11 +887,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
887887
}
888888

889889
private: //Internal Helper functions
890-
///@brief Writes out the verilog netlist
891-
void print_verilog(int depth = 0) {
892-
verilog_os_ << indent(depth) << "//Verilog generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n";
893-
verilog_os_ << indent(depth) << "module " << top_module_name_ << " (\n";
894-
890+
virtual void print_primary_io(int depth) {
895891
//Primary Inputs
896892
for (auto iter = inputs_.begin(); iter != inputs_.end(); ++iter) {
897893
verilog_os_ << indent(depth + 1) << "input " << escape_verilog_identifier(*iter);
@@ -900,7 +896,6 @@ class NetlistWriterVisitor : public NetlistVisitor {
900896
}
901897
verilog_os_ << "\n";
902898
}
903-
904899
//Primary Outputs
905900
for (auto iter = outputs_.begin(); iter != outputs_.end(); ++iter) {
906901
verilog_os_ << indent(depth + 1) << "output " << escape_verilog_identifier(*iter);
@@ -909,6 +904,22 @@ class NetlistWriterVisitor : public NetlistVisitor {
909904
}
910905
verilog_os_ << "\n";
911906
}
907+
}
908+
909+
virtual void print_assignments(int depth) {
910+
verilog_os_ << "\n";
911+
verilog_os_ << indent(depth + 1) << "//IO assignments\n";
912+
for (auto& assign : assignments_) {
913+
assign.print_verilog(verilog_os_, indent(depth + 1));
914+
}
915+
}
916+
917+
///@brief Writes out the verilog netlist
918+
void print_verilog(int depth = 0) {
919+
verilog_os_ << indent(depth) << "//Verilog generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n";
920+
verilog_os_ << indent(depth) << "module " << top_module_name_ << " (\n";
921+
922+
print_primary_io(depth);
912923
verilog_os_ << indent(depth) << ");\n";
913924

914925
//Wire declarations
@@ -924,11 +935,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
924935
}
925936

926937
//connections between primary I/Os and their internal wires
927-
verilog_os_ << "\n";
928-
verilog_os_ << indent(depth + 1) << "//IO assignments\n";
929-
for (auto& assign : assignments_) {
930-
assign.print_verilog(verilog_os_, indent(depth + 1));
931-
}
938+
print_assignments(depth);
932939

933940
//Interconnect between cell instances
934941
verilog_os_ << "\n";

0 commit comments

Comments
 (0)