vpr: base: netlist writer: refactor verilog writer

Signed-off-by: Pawel Czarnecki <[email protected]>

Author: lpawelcz

vpr/src/base/netlist_writer.cpp

@@ -887,11 +887,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
     }
 
   private: //Internal Helper functions
-    ///@brief Writes out the verilog netlist
-    void print_verilog(int depth = 0) {
-        verilog_os_ << indent(depth) << "//Verilog generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n";
-        verilog_os_ << indent(depth) << "module " << top_module_name_ << " (\n";
-
+    virtual void print_primary_io(int depth) {
         //Primary Inputs
         for (auto iter = inputs_.begin(); iter != inputs_.end(); ++iter) {
             verilog_os_ << indent(depth + 1) << "input " << escape_verilog_identifier(*iter);
@@ -900,7 +896,6 @@ class NetlistWriterVisitor : public NetlistVisitor {
             }
             verilog_os_ << "\n";
         }
-
         //Primary Outputs
         for (auto iter = outputs_.begin(); iter != outputs_.end(); ++iter) {
             verilog_os_ << indent(depth + 1) << "output " << escape_verilog_identifier(*iter);
@@ -909,6 +904,22 @@ class NetlistWriterVisitor : public NetlistVisitor {
             }
             verilog_os_ << "\n";
         }
+    }
+
+    virtual void print_assignments(int depth) {
+        verilog_os_ << "\n";
+        verilog_os_ << indent(depth + 1) << "//IO assignments\n";
+        for (auto& assign : assignments_) {
+            assign.print_verilog(verilog_os_, indent(depth + 1));
+        }
+    }
+
+    ///@brief Writes out the verilog netlist
+    void print_verilog(int depth = 0) {
+        verilog_os_ << indent(depth) << "//Verilog generated by VPR " << vtr::VERSION << " from post-place-and-route implementation\n";
+        verilog_os_ << indent(depth) << "module " << top_module_name_ << " (\n";
+
+        print_primary_io(depth);
         verilog_os_ << indent(depth) << ");\n";
 
         //Wire declarations
@@ -924,11 +935,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
         }
 
         //connections between primary I/Os and their internal wires
-        verilog_os_ << "\n";
-        verilog_os_ << indent(depth + 1) << "//IO assignments\n";
-        for (auto& assign : assignments_) {
-            assign.print_verilog(verilog_os_, indent(depth + 1));
-        }
+        print_assignments(depth);
 
         //Interconnect between cell instances
         verilog_os_ << "\n";