Merge pull request #2002 from antmicro/fix-post-verilog-port-handling

Corrected handling of unconnected ports in output Verilog netlist

Author: acomodi

vpr/src/base/netlist_writer.cpp

@@ -127,6 +127,9 @@ std::string join_identifier(std::string lhs, std::string rhs);
 //
 //
 
+// Unconnected net prefix
+const std::string unconn_prefix = "__vpr__unconn";
+
 //A combinational timing arc
 class Arc {
   public:
@@ -953,6 +956,16 @@ class NetlistWriterVisitor : public NetlistVisitor {
             inst->print_verilog(verilog_os_, unconn_count, depth + 1);
         }
 
+        //Unconnected wires
+        if (unconn_count) {
+            verilog_os_ << "\n";
+            verilog_os_ << indent(depth + 1) << "//Unconnected wires\n";
+            for (size_t i = 0; i < unconn_count; ++i) {
+                auto name = unconn_prefix + std::to_string(i);
+                verilog_os_ << indent(depth + 1) << "wire " << escape_verilog_identifier(name) << ";\n";
+            }
+        }
+
         verilog_os_ << "\n";
         verilog_os_ << indent(depth) << "endmodule\n";
     }
@@ -2134,7 +2147,7 @@ double get_delay_ps(double delay_sec) {
 std::string create_unconn_net(size_t& unconn_count) {
     //We increment unconn_count by reference so each
     //call generates a unique name
-    return "__vpr__unconn" + std::to_string(unconn_count++);
+    return unconn_prefix + std::to_string(unconn_count++);
 }
 
 /**
@@ -2177,6 +2190,30 @@ void print_blif_port(std::ostream& os, size_t& unconn_count, const std::string&
  * Handles special cases like multi-bit and disconnected ports
  */
 void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::string& port_name, const std::vector<std::string>& nets, PortType type, int depth, struct t_analysis_opts& opts) {
+    auto unconn_inp_name = [&]() {
+        switch (opts.post_synth_netlist_unconn_input_handling) {
+            case e_post_synth_netlist_unconn_handling::GND:
+                return std::string("1'b0");
+            case e_post_synth_netlist_unconn_handling::VCC:
+                return std::string("1'b1");
+            case e_post_synth_netlist_unconn_handling::NETS:
+                return create_unconn_net(unconn_count);
+            case e_post_synth_netlist_unconn_handling::UNCONNECTED:
+            default:
+                return std::string("1'bX");
+        }
+    };
+
+    auto unconn_out_name = [&]() {
+        switch (opts.post_synth_netlist_unconn_output_handling) {
+            case e_post_synth_netlist_unconn_handling::NETS:
+                return create_unconn_net(unconn_count);
+            case e_post_synth_netlist_unconn_handling::UNCONNECTED:
+            default:
+                return std::string();
+        }
+    };
+
     //Port name
     os << indent(depth) << "." << port_name << "(";
 
@@ -2186,60 +2223,57 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
         if (nets[0].empty()) {
             //Disconnected
             if (type == PortType::INPUT || type == PortType::CLOCK) {
-                switch (opts.post_synth_netlist_unconn_input_handling) {
-                    case e_post_synth_netlist_unconn_handling::GND:
-                        os << "1'b0";
-                        break;
-                    case e_post_synth_netlist_unconn_handling::VCC:
-                        os << "1'b1";
-                        break;
-                    case e_post_synth_netlist_unconn_handling::NETS:
-                        os << create_unconn_net(unconn_count);
-                        break;
-                    case e_post_synth_netlist_unconn_handling::UNCONNECTED:
-                    default:
-                        os << "1'bX";
-                }
+                os << unconn_inp_name();
             } else {
                 VTR_ASSERT(type == PortType::OUTPUT);
-                switch (opts.post_synth_netlist_unconn_output_handling) {
-                    case e_post_synth_netlist_unconn_handling::NETS:
-                        os << create_unconn_net(unconn_count);
-                        break;
-                    case e_post_synth_netlist_unconn_handling::UNCONNECTED:
-                    default:
-                        os << "1'bX";
-                }
+                os << unconn_out_name();
             }
         } else {
             //Connected
             os << escape_verilog_identifier(nets[0]);
         }
     } else {
+        // Check if all pins are unconnected
+        bool all_unconnected = true;
+        for (size_t i = 0; i < nets.size(); ++i) {
+            if (!nets[i].empty()) {
+                all_unconnected = false;
+                break;
+            }
+        }
+
         //A multi-bit port, we explicitly concat the single-bit nets to build the port,
         //taking care to print MSB on left and LSB on right
-        os << "{"
-           << "\n";
-        for (int ipin = (int)nets.size() - 1; ipin >= 0; --ipin) { //Reverse order to match endianess
-            os << indent(depth + 1);
-            if (nets[ipin].empty()) {
-                //Disconnected
-                if (type == PortType::INPUT || type == PortType::CLOCK) {
-                    os << "1'b0";
+        if (all_unconnected && type == PortType::OUTPUT && opts.post_synth_netlist_unconn_output_handling == e_post_synth_netlist_unconn_handling::UNCONNECTED) {
+            // Empty connection
+        } else {
+            // Individual bits
+            os << "{"
+               << "\n";
+            for (int ipin = (int)nets.size() - 1; ipin >= 0; --ipin) { //Reverse order to match endianess
+                os << indent(depth + 1);
+                if (nets[ipin].empty()) {
+                    //Disconnected
+                    if (type == PortType::INPUT || type == PortType::CLOCK) {
+                        os << unconn_inp_name();
+                    } else {
+                        VTR_ASSERT(type == PortType::OUTPUT);
+                        // When concatenating output connection there cannot
+                        // be an empty placeholder so we have to create a
+                        // dummy net.
+                        os << create_unconn_net(unconn_count);
+                    }
                 } else {
-                    VTR_ASSERT(type == PortType::OUTPUT);
-                    os << "";
+                    //Connected
+                    os << escape_verilog_identifier(nets[ipin]);
+                }
+                if (ipin != 0) {
+                    os << ",";
                 }
-            } else {
-                //Connected
-                os << escape_verilog_identifier(nets[ipin]);
-            }
-            if (ipin != 0) {
-                os << ",";
                 os << "\n";
             }
+            os << indent(depth) + " }";
         }
-        os << "}";
     }
     os << ")";
 }

vpr/test/test_post_verilog.cpp

@@ -0,0 +1,91 @@
+#include "catch2/catch_test_macros.hpp"
+
+#include "vpr_api.h"
+#include "timing_place_lookup.h"
+
+#include <fstream>
+
+namespace {
+
+static constexpr const char kArchFile[] = "test_post_verilog_arch.xml";
+static constexpr const char kCircuitFile[] = "unconnected.eblif";
+
+void do_vpr_flow(const char* input_unc_opt, const char* output_unc_opt) {
+    // Minimal setup
+    auto options = t_options();
+    auto arch = t_arch();
+    auto vpr_setup = t_vpr_setup();
+
+    // Command line arguments
+    const char* argv[] = {
+        "test_vpr",
+        kArchFile,
+        kCircuitFile,
+        "--route_chan_width", "100",
+        "--gen_post_synthesis_netlist", "on",
+        "--post_synth_netlist_unconn_inputs", input_unc_opt,
+        "--post_synth_netlist_unconn_outputs", output_unc_opt};
+
+    vpr_init(sizeof(argv) / sizeof(argv[0]), argv,
+             &options, &vpr_setup, &arch);
+
+    bool flow_succeeded = vpr_flow(vpr_setup, arch);
+
+    free_routing_structs();
+    vpr_free_all(arch, vpr_setup);
+
+    REQUIRE(flow_succeeded == true);
+}
+
+void compare_files(const std::string& output_fname, const std::string& golden_fname) {
+    printf("Comparing '%s' vs. '%s'\n", output_fname.c_str(), golden_fname.c_str());
+
+    std::ifstream output_file(output_fname);
+    std::ifstream golden_file(golden_fname);
+
+    REQUIRE(output_file.good());
+    REQUIRE(golden_file.good());
+
+    auto read_lines = [](std::ifstream& fp) {
+        std::vector<std::string> lines;
+        while (fp.good()) {
+            std::string line;
+            std::getline(fp, line);
+            lines.push_back(line);
+        }
+
+        return lines;
+    };
+
+    auto output_data = read_lines(output_file);
+    auto golden_data = read_lines(golden_file);
+
+    REQUIRE(!output_data.empty());
+    REQUIRE(!golden_data.empty());
+    REQUIRE(output_data.size() == golden_data.size());
+
+    // Skip the first line as it contains a comment with build SHA
+    output_data.erase(output_data.begin());
+    golden_data.erase(golden_data.begin());
+
+    REQUIRE(output_data == golden_data);
+}
+
+TEST_CASE("post_verilog", "[vpr]") {
+    do_vpr_flow("unconnected", "unconnected");
+    compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_unconnected_o_unconnected.golden.v");
+
+    do_vpr_flow("unconnected", "nets");
+    compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_unconnected_o_nets.golden.v");
+
+    do_vpr_flow("vcc", "unconnected");
+    compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_vcc_o_unconnected.golden.v");
+
+    do_vpr_flow("gnd", "unconnected");
+    compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_gnd_o_unconnected.golden.v");
+
+    do_vpr_flow("nets", "unconnected");
+    compare_files("unconnected_post_synthesis.v", "test_post_verilog_i_nets_o_unconnected.golden.v");
+}
+
+} // namespace