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[vpr] syntax
1 parent d338952 commit ba0576d

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3 files changed

+19
-13
lines changed

3 files changed

+19
-13
lines changed

vpr/src/tileable_rr_graph/rr_gsb.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1181,3 +1181,8 @@ bool RRGSB::validate_ipin_node_id(const e_side& side, const size_t& node_id) con
11811181
bool RRGSB::validate_cb_type(const t_rr_type& cb_type) const {
11821182
return ((CHANX == cb_type) || (CHANY == cb_type));
11831183
}
1184+
1185+
size_t RRGSB::get_cb_opin_type_id(const t_rr_type& cb_type) const {
1186+
VTR_ASSERT(validate_cb_type(cb_type));
1187+
return cb_type == CHANX ? 0 : 1;
1188+
}

vpr/src/tileable_rr_graph/rr_gsb.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,6 +229,7 @@ class RRGSB {
229229
bool validate_opin_node_id(const e_side& side, const size_t& node_id) const;
230230
bool validate_ipin_node_id(const e_side& side, const size_t& node_id) const;
231231
bool validate_cb_type(const t_rr_type& cb_type) const;
232+
size_t get_cb_opin_type_id(const t_rr_type& cb_type) const;
232233

233234
private: /* Internal Data */
234235
/* Coordinator */

vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -637,16 +637,16 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
637637
* - bottom side routing tracks for any GSB exist on y = [0, H)
638638
* - left side routing tracks for any GSB exist on x = [0, W)
639639
*/
640-
size_t std::map<e_side, vtr:Point<size_t>> track_range;
641-
track_range[TOP] = vtr:Point<size_t>(0, grids.height() - 2);
642-
track_range[RIGHT] = vtr:Point<size_t>(0, grids.width() - 2);
643-
track_range[BOTTOM] = vtr:Point<size_t>(1, grids.height() - 2);
644-
track_range[LEFT] = vtr:Point<size_t>(1, grids.width() - 2);
640+
std::map<e_side, vtr::Point<size_t>> track_range;
641+
track_range[TOP] = vtr::Point<size_t>(0, grids.height() - 2);
642+
track_range[RIGHT] = vtr::Point<size_t>(0, grids.width() - 2);
643+
track_range[BOTTOM] = vtr::Point<size_t>(1, grids.height() - 2);
644+
track_range[LEFT] = vtr::Point<size_t>(1, grids.width() - 2);
645645
if (perimeter_cb) {
646-
track_range[TOP] = vtr:Point<size_t>(0, grids.height() - 1);
647-
track_range[RIGHT] = vtr:Point<size_t>(0, grids.width() - 1);
648-
track_range[BOTTOM] = vtr:Point<size_t>(0, grids.height());
649-
track_range[LEFT] = vtr:Point<size_t>(0, grids.width());
646+
track_range[TOP] = vtr::Point<size_t>(0, grids.height() - 1);
647+
track_range[RIGHT] = vtr::Point<size_t>(0, grids.width() - 1);
648+
track_range[BOTTOM] = vtr::Point<size_t>(0, grids.height());
649+
track_range[LEFT] = vtr::Point<size_t>(0, grids.width());
650650
}
651651

652652
/* Create an object to return */
@@ -684,7 +684,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
684684
switch (side) {
685685
case TOP: /* TOP = 0 */
686686
/* For the border, we should take special care. The top column (H-1) does not have any top side routing channel. Any lower column may have (<= H-2) */
687-
if (track_range[side].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side].y()) {
687+
if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) {
688688
rr_gsb.clear_one_side(side_manager.get_side());
689689
break;
690690
}
@@ -714,7 +714,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
714714
break;
715715
case RIGHT: /* RIGHT = 1 */
716716
/* For the border, we should take special care. The rightmost column (W-1) does not have any right side routing channel. If perimeter connection block is not enabled, even the last second rightmost column (W-2) does not have any right side routing channel */
717-
if (track_range[side].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side].y()) {
717+
if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) {
718718
rr_gsb.clear_one_side(side_manager.get_side());
719719
break;
720720
}
@@ -744,7 +744,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
744744
break;
745745
case BOTTOM: /* BOTTOM = 2*/
746746
/* For the border, we should take special care */
747-
if (track_range[side].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side].y()) {
747+
if (track_range[side_manager.get_side()].x() > gsb_coordinate.y() || gsb_coordinate.y() >= track_range[side_manager.get_side()].y()) {
748748
rr_gsb.clear_one_side(side_manager.get_side());
749749
break;
750750
}
@@ -774,7 +774,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
774774
break;
775775
case LEFT: /* LEFT = 3 */
776776
/* For the border, we should take special care */
777-
if (track_range[side].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side].y()) {
777+
if (track_range[side_manager.get_side()].x() > gsb_coordinate.x() || gsb_coordinate.x() >= track_range[side_manager.get_side()].y()) {
778778
rr_gsb.clear_one_side(side_manager.get_side());
779779
break;
780780
}

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