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nasrineshraghijeanlego
nasrineshraghi
authored and
jeanlego
committed
ODIN_II language coverage: part-select keyword (#511)
* Add part-select keyword as a language coverage * new line at the end of the file * Update Documentation according to index part-select * added range checking to part-selct operator * refactored newPartSelectRangeRef into newRangeRef * added limits calculations * Add test bench for part-select * hotfix for part-select range * Add test * fixed -: index calculation * add error message * change in error message * change the error messages * Fix the messages * latest change
1 parent d4771a1 commit b7db9e8

16 files changed

+158
-5
lines changed

‎ODIN_II/README.rst

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@@ -309,8 +309,10 @@ Verilog Synthesizable Keyword Support:
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+-------------------+------------------+---------------------+--------------------+
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| macromodule | | | |
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+-------------------+------------------+---------------------+--------------------+
312-
313-
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| +: | | | |
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+-------------------+------------------+---------------------+--------------------+
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| -: | | | |
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+-------------------+------------------+---------------------+--------------------+
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Verilog NON-Synthesizable Keyword Support:
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*********************************

‎ODIN_II/SRC/include/ast_util.h

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@@ -24,6 +24,7 @@ void make_concat_into_list_of_strings(ast_node_t *concat_top, char *instance_nam
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void change_to_number_node(ast_node_t *node, long number);
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int get_range(ast_node_t* first_node);
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char *get_name_of_pin_at_bit(ast_node_t *var_node, int bit, char *instance_name_prefix);
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char *get_name_of_var_declare_at_bit(ast_node_t *var_declare, int bit);
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char_list_t *get_name_of_pins(ast_node_t *var_node, char *instance_name_prefix);

‎ODIN_II/SRC/include/parse_making_ast.h

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@@ -21,6 +21,8 @@ ast_node_t *markAndProcessSymbolListWith(ids top_type, ids id, ast_node_t *symbo
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ast_node_t *newArrayRef(char *id, ast_node_t *expression, int line_number);
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ast_node_t *newArrayRef2D(char *id, ast_node_t *expression1, ast_node_t *expression2, int line_number);
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ast_node_t *newRangeRef(char *id, ast_node_t *expression1, ast_node_t *expression2, int line_number);
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ast_node_t *newPartSelectRangeRef(char *id, ast_node_t *expression1, ast_node_t *expression2, char direction,
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int line_number);
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ast_node_t *newRangeRef2D(char *id, ast_node_t *expression1, ast_node_t *expression2, ast_node_t *expression3, ast_node_t *expression4, int line_number);
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ast_node_t *newBinaryOperation(operation_list op_id, ast_node_t *expression1, ast_node_t *expression2, int line_number);
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ast_node_t *newExpandPower(operation_list op_id, ast_node_t *expression1, ast_node_t *expression2, int line_number);

‎ODIN_II/SRC/parse_making_ast.cpp

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@@ -835,6 +835,54 @@ ast_node_t *newRangeRef(char *id, ast_node_t *expression1, ast_node_t *expressio
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return new_node;
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}
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/*---------------------------------------------------------------------------------------------
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* (function: newPartSelectRangeRef)
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*-------------------------------------------------------------------------------------------*/
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ast_node_t *newPartSelectRangeRef(char *id, ast_node_t *expression1, ast_node_t *expression2, char direction,
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int line_number)
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{
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long sc_spot;
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oassert(expression1 != NULL && expression1->type == NUMBERS && expression2 != NULL && expression2->type == NUMBERS);
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/* Try to find the original array to check low/high indices */
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if ((sc_spot = sc_lookup_string(modules_inputs_sc, id)) == -1 &&
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(sc_spot = sc_lookup_string(modules_outputs_sc, id)) == -1){
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error_message(PARSE_ERROR, line_number, current_parse_file, "Could not find variable %s", id);
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return nullptr;
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}
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ast_node_t *original_range = (ast_node_t *) modules_inputs_sc->data[sc_spot];;
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long upper_limit = original_range->children[1]->types.number.value;
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long bottom_limit = original_range->children[2]->types.number.value;
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if (expression1->types.number.value < 0 || expression2->types.number.value < 0){
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/* Negetive numbers are not supported */
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error_message(PARSE_ERROR, line_number, current_parse_file,
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"Odin doesn't support negative number in index : %s[%d%s%d].", id,
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expression1->types.number.value, direction == 1 ? "+:" : "-:",
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expression2->types.number.value);
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}
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if (direction == 1){
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expression1->types.number.value = expression1->types.number.value + expression2->types.number.value - 1;
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expression2->types.number.value = expression1->types.number.value - expression2->types.number.value + 1;
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}
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else{
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expression2->types.number.value = expression1->types.number.value - expression2->types.number.value + 1;
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}
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if (expression1->types.number.value > upper_limit || expression2->types.number.value < bottom_limit) {
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/* out of original range */
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error_message(PARSE_ERROR, line_number,current_parse_file,
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"This part-select range %s:[%d%s%d] is out of range. It should be in the %s:[%d:%d] range.",
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id,expression1->types.number.value, direction ==1 ? "+:" : "-:",expression2->types.number.value,
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id,upper_limit,bottom_limit );
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}
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return newRangeRef(id, expression1, expression2, line_number);
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}
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/*---------------------------------------------------------------------------------------------
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* (function: newBinaryOperation)
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*-------------------------------------------------------------------------------------------*/

‎ODIN_II/SRC/verilog_bison.y

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@@ -65,7 +65,8 @@ int yylex(void);
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%token vOUTPUT vPARAMETER vPOSEDGE vREG vWIRE vXNOR vXOR vDEFPARAM voANDAND
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%token voOROR voLTE voGTE voPAL voSLEFT voSRIGHT vo ASRIGHT voEQUAL voNOTEQUAL voCASEEQUAL
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%token voCASENOTEQUAL voXNOR voNAND voNOR vWHILE vINTEGER
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%token vNOT_SUPPORT
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%token vNOT_SUPPORT
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%token vPLUS_COLON vMINUS_COLON
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%token '?' ':' '|' '^' '&' '<' '>' '+' '-' '*' '/' '%' '(' ')' '{' '}' '[' ']'
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%right '?' ':'
@@ -510,6 +511,8 @@ primary:
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| vSYMBOL_ID {$$ = newSymbolNode($1, yylineno);}
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| vSYMBOL_ID '[' expression ']' {$$ = newArrayRef($1, $3, yylineno);}
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| vSYMBOL_ID '[' expression ']' '[' expression ']' {$$ = newArrayRef2D($1, $3, $6, yylineno);}
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| vSYMBOL_ID '[' expression vPLUS_COLON expression ']' {$$ = newPartSelectRangeRef($1, $3, $5, 1, yylineno);}
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| vSYMBOL_ID '[' expression vMINUS_COLON expression ']' {$$ = newPartSelectRangeRef($1, $3, $5, -1, yylineno);}
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| vSYMBOL_ID '[' expression ':' expression ']' {$$ = newRangeRef($1, $3, $5, yylineno);}
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| vSYMBOL_ID '[' expression ':' expression ']' '[' expression ':' expression ']' {$$ = newRangeRef2D($1, $3, $5, $8, $10, yylineno);}
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| '{' probable_expression_list '}' {$$ = $2; ($2)->types.concat.num_bit_strings = -1;}

‎ODIN_II/SRC/verilog_flex.l

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@@ -175,11 +175,12 @@ char* standardize_number(const char* input);
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<INITIAL>"~^" { MP; return voXNOR;}
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<INITIAL>"~&" { MP; return voNAND;}
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<INITIAL>"~|" { MP; return voNOR;}
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<INITIAL>"+:" { MP; return vPLUS_COLON;}
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<INITIAL>"-:" { MP; return vMINUS_COLON;}
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/* unsupported Operators */
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<INITIAL>"&&&" { MP; return vNOT_SUPPORT;}
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<INITIAL>"+:" { MP; return vNOT_SUPPORT;}
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<INITIAL>"-:" { MP; return vNOT_SUPPORT;}
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/* operands */

‎ODIN_II/regression_test/benchmark/operators/minuscolon_6_bit.v

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@@ -0,0 +1,11 @@
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module OR2in (A,B,C1,C2);
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input [5:0] A ;
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input [5:0] B ;
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output [2:0] C1 ;
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output [2:0] C2 ;
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8+
assign C1=A[2-:3] | B[2-:3] ;
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assign C2=A[5-:3] | B[5-:3] ;
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endmodule

‎ODIN_II/regression_test/benchmark/operators/minuscolon_6_bit_input

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GLOBAL_SIM_BASE_CLK A B
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0 0X20 0X26
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0 0X2C 0X16
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0 0X3C 0X36
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0 0X22 0X06
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0 0X24 0X20
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0 0X01 0X06
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0 0X0C 0X07
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0 0X01 0X26
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0 0X21 0X06
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0 0X0C 0X26
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‎ODIN_II/regression_test/benchmark/operators/minuscolon_6_bit_output

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C1 C2
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0X06 0X04
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0X06 0X07
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0X06 0X07
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0X06 0X04
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0x04 0x04
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0x07 0x00
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0x07 0x01
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0x07 0x04
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0x07 0x04
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0x06 0x05

‎ODIN_II/regression_test/benchmark/operators/pluscolon_6_bit.v

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@@ -0,0 +1,11 @@
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module And2in (A,B,C1,C2);
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input [5:0] A ;
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input [5:0] B ;
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output [2:0] C1 ;
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output [2:0] C2 ;
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assign C1 = A[0+:3] & B[0+:3] ;
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assign C2 = A[-3+:3] & B[3+:3] ;
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endmodule

‎ODIN_II/regression_test/benchmark/operators/pluscolon_6_bit_input

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@@ -0,0 +1,5 @@
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GLOBAL_SIM_BASE_CLK A B
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0 0X27 0X1A
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0 0X28 0X32
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0 0X10 0X3F
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0 0X1D 0X3F

‎ODIN_II/regression_test/benchmark/operators/pluscolon_6_bit_output

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@@ -0,0 +1,7 @@
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C1 C2
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0X2 0X0
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0X0 0X4
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0X0 0X2
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0X5 0X3
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‎ODIN_II/regression_test/benchmark/operators/pluscolon_8_bit.v

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@@ -0,0 +1,11 @@
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module And2in (A,B,C1,C2);
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input [7:0] A ;
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input [7:0] B ;
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output [3:0] C1 ;
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output [3:0] C2 ;
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assign C1=A[0+:4] & B[0+:4] ;
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assign C2=A[3+:5] & B[3+:5] ;
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endmodule

‎ODIN_II/regression_test/benchmark/operators/pluscolon_8_bit_input

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GLOBAL_SIM_BASE_CLK A B
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0 0X60 0XA6
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0 0XEC 0X16
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0 0XBC 0XB6
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0 0X62 0X46
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0 0XE4 0X20
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0 0X01 0X86
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0 0XCC 0X47
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0 0X41 0XE6
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0 0XE1 0X06
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0 0XCC 0XE6

‎ODIN_II/regression_test/benchmark/operators/pluscolon_8_bit_output

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C1 C2
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0X0 0X4
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0X4 0X0
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0X4 0X6
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0X2 0X8
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0X0 0X4
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0X0 0X0
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0X4 0X8
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0X0 0X8
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0X0 0X0
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0X4 0X8
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‎doc/src/odin/index.rst

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@@ -309,6 +309,11 @@ Verilog Synthesizable Keyword Support:
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+-------------------+------------------+---------------------+--------------------+
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| macromodule | | | |
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+-------------------+------------------+---------------------+--------------------+
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| +: | | | |
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+-------------------+------------------+---------------------+--------------------+
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| -: | | | |
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+-------------------+------------------+---------------------+--------------------+
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Verilog NON-Synthesizable Keyword Support:

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