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Merge pull request #1728 from ArashAhmadian/vtr_tasks_reorganization
Reorganizing vtr_flow/tasks
2 parents 083f875 + dc47444 commit a7ae65d

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‎.github/kokoro/presubmit/nightly.cfg renamed to ‎.github/kokoro/presubmit/nightly_test1.cfg

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ env_vars {
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env_vars {
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key: "VTR_TEST"
54-
value: "vtr_reg_nightly"
54+
value: "vtr_reg_nightly_test1"
5555
}
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5757
#Options for run_reg_test.py
@@ -63,5 +63,5 @@ env_vars {
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env_vars {
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key: "NUM_CORES"
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value: "3"
66+
value: "8"
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}

‎.github/kokoro/presubmit/nightly_test2.cfg

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# Format: //devtools/kokoro/config/proto/build.proto
2+
3+
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
4+
5+
# 72 hours
6+
timeout_mins: 4320
7+
8+
action {
9+
define_artifacts {
10+
# File types
11+
regex: "**/*.out"
12+
regex: "**/vpr_stdout.log"
13+
regex: "**/parse_results.txt"
14+
regex: "**/qor_results.txt"
15+
regex: "**/pack.log"
16+
regex: "**/place.log"
17+
regex: "**/route.log"
18+
regex: "**/*_qor.csv"
19+
regex: "**/*.out.gz"
20+
regex: "**/vpr_stdout.log.gz"
21+
regex: "**/parse_results.txt.gz"
22+
regex: "**/qor_results.txt.gz"
23+
regex: "**/pack.log.gz"
24+
regex: "**/place.log.gz"
25+
regex: "**/route.log.gz"
26+
regex: "**/*_qor.csv.gz"
27+
strip_prefix: "github/vtr-verilog-to-routing/"
28+
}
29+
}
30+
31+
env_vars {
32+
key: "KOKORO_TYPE"
33+
value: "presubmit"
34+
}
35+
36+
env_vars {
37+
key: "KOKORO_DIR"
38+
value: "vtr-verilog-to-routing"
39+
}
40+
41+
env_vars {
42+
key: "VTR_DIR"
43+
value: "vtr-verilog-to-routing"
44+
}
45+
46+
#Use default build configuration
47+
env_vars {
48+
key: "VTR_CMAKE_PARAMS"
49+
value: ""
50+
}
51+
52+
env_vars {
53+
key: "VTR_TEST"
54+
value: "vtr_reg_nightly_test2"
55+
}
56+
57+
#Options for run_reg_test.py
58+
# -show_failures: show tool failures in main log output
59+
env_vars {
60+
key: "VTR_TEST_OPTIONS"
61+
value: "-show_failures"
62+
}
63+
64+
env_vars {
65+
key: "NUM_CORES"
66+
value: "8"
67+
}

‎.github/kokoro/presubmit/nightly_test3.cfg

Lines changed: 67 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,67 @@
1+
# Format: //devtools/kokoro/config/proto/build.proto
2+
3+
build_file: "vtr-verilog-to-routing/.github/kokoro/run-vtr.sh"
4+
5+
# 72 hours
6+
timeout_mins: 4320
7+
8+
action {
9+
define_artifacts {
10+
# File types
11+
regex: "**/*.out"
12+
regex: "**/vpr_stdout.log"
13+
regex: "**/parse_results.txt"
14+
regex: "**/qor_results.txt"
15+
regex: "**/pack.log"
16+
regex: "**/place.log"
17+
regex: "**/route.log"
18+
regex: "**/*_qor.csv"
19+
regex: "**/*.out.gz"
20+
regex: "**/vpr_stdout.log.gz"
21+
regex: "**/parse_results.txt.gz"
22+
regex: "**/qor_results.txt.gz"
23+
regex: "**/pack.log.gz"
24+
regex: "**/place.log.gz"
25+
regex: "**/route.log.gz"
26+
regex: "**/*_qor.csv.gz"
27+
strip_prefix: "github/vtr-verilog-to-routing/"
28+
}
29+
}
30+
31+
env_vars {
32+
key: "KOKORO_TYPE"
33+
value: "presubmit"
34+
}
35+
36+
env_vars {
37+
key: "KOKORO_DIR"
38+
value: "vtr-verilog-to-routing"
39+
}
40+
41+
env_vars {
42+
key: "VTR_DIR"
43+
value: "vtr-verilog-to-routing"
44+
}
45+
46+
#Use default build configuration
47+
env_vars {
48+
key: "VTR_CMAKE_PARAMS"
49+
value: ""
50+
}
51+
52+
env_vars {
53+
key: "VTR_TEST"
54+
value: "vtr_reg_nightly_test3"
55+
}
56+
57+
#Options for run_reg_test.py
58+
# -show_failures: show tool failures in main log output
59+
env_vars {
60+
key: "VTR_TEST_OPTIONS"
61+
value: "-show_failures"
62+
}
63+
64+
env_vars {
65+
key: "NUM_CORES"
66+
value: "8"
67+
}

‎.github/kokoro/steps/vtr-test.sh

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,10 @@ find vtr_flow/benchmarks/titan_blif/ -type f -not -name 'README.*' -delete
6969
find . -type f -regex ".*\.tar\.\(gz\|xz\)" -delete
7070

7171
#Gzip output files from vtr_reg_nightly tests to lower working directory disk space
72-
find vtr_flow/tasks/regression_tests/vtr_reg_nightly/ -type f -print0 | xargs -0 -P $(nproc) gzip
72+
find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test1/ -type f -print0 | xargs -0 -P $(nproc) gzip
73+
find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test2/ -type f -print0 | xargs -0 -P $(nproc) gzip
74+
find vtr_flow/tasks/regression_tests/vtr_reg_nightly_test3/ -type f -print0 | xargs -0 -P $(nproc) gzip
75+
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7477
# Make sure working directory doesn't exceed disk space limit!
7578
echo "Working directory size: $(du -sh)"

‎README.developers.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -754,12 +754,12 @@ There may be times when a regression test fails its QoR test because its golden_
754754
2. Next, generate new golden reference results using `parse_vtr_task.py` and the `-create_golden` option.
755755

756756
```shell
757-
$ ../scripts/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -create_golden
757+
$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -create_golden
758758
```
759759
3. Lastly, check that the results match with the `-check_golden` option
760760

761761
```shell
762-
$ ../scripts/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -check_golden
762+
$ ../scripts/python_libs/vtr/parse_vtr_task.py regression_tests/vtr_reg_nightly/vtr_ex_test -check_golden
763763
```
764764
Once the `-check_golden` command passes, the changes to the golden result can be committed so that the reg test will pass in future runs of vtr_reg_nightly.
765765

‎vtr_flow/arch/timing/fixed_size/fixed_k6_N8_gate_boost_0.2V_22nm.xml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
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<!-- ODIN II specific config ends -->
133133
<!-- Physical descriptions begin -->
134134
<layout>
135-
<device_layout name="unnamed_device" width="17" height="17">
135+
<fixed_layout name="unnamed_device" width="17" height="17">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
137137
<perimeter type="io" priority="100"/>
138138
<corners type="EMPTY" priority="101"/>
@@ -144,7 +144,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
144144
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
145145
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
146146
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
147-
</device_layout>
147+
</fixed_layout>
148148
</layout>
149149
<device>
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<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_chain_gate_boost_0.2V_22nm.xml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
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<!-- ODIN II specific config ends -->
157157
<!-- Physical descriptions begin -->
158158
<layout>
159-
<device_layout name="unnamed_device" width="17" height="17">
159+
<fixed_layout name="unnamed_device" width="17" height="17">
160160
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
161161
<perimeter type="io" priority="100"/>
162162
<corners type="EMPTY" priority="101"/>
@@ -168,7 +168,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
168168
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
169169
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
170170
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
171-
</device_layout>
171+
</fixed_layout>
172172
</layout>
173173
<device>
174174
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_N8_lookahead_unbalanced_chain_gate_boost_0.2V_22nm.xml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -159,7 +159,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
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<!-- ODIN II specific config ends -->
160160
<!-- Physical descriptions begin -->
161161
<layout>
162-
<device_layout name="unnamed_device" width="17" height="17">
162+
<fixed_layout name="unnamed_device" width="17" height="17">
163163
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
164164
<perimeter type="io" priority="100"/>
165165
<corners type="EMPTY" priority="101"/>
@@ -171,7 +171,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
171171
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
172172
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
173173
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
174-
</device_layout>
174+
</fixed_layout>
175175
</layout>
176176
<device>
177177
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_N8_ripple_chain_gate_boost_0.2V_22nm.xml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -156,7 +156,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
156156
<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
158158
<layout>
159-
<device_layout name="unnamed_device" width="17" height="17">
159+
<fixed_layout name="unnamed_device" width="17" height="17">
160160
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
161161
<perimeter type="io" priority="100"/>
162162
<corners type="EMPTY" priority="101"/>
@@ -168,7 +168,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
168168
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
169169
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
170170
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
171-
</device_layout>
171+
</fixed_layout>
172172
</layout>
173173
<device>
174174
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_N8_unbalanced_ripple_chain_gate_boost_0.2V_22nm.xml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -158,7 +158,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout>
161-
<device_layout name="unnamed_device" width="17" height="17">
161+
<fixed_layout name="unnamed_device" width="17" height="17">
162162
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
163163
<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
@@ -170,7 +170,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
170170
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
171171
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
172172
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
173-
</device_layout>
173+
</fixed_layout>
174174
</layout>
175175
<device>
176176
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2ripple_N8_22nm.xml

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,8 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
117117
</fc>
118118
<pinlocations pattern="custom">
119119
<loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
120-
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
120+
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
121+
<loc side="top">clb.cin</loc>
121122
</pinlocations>
122123
</sub_tile>
123124
</tile>
@@ -153,7 +154,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
153154
<!-- ODIN II specific config ends -->
154155
<!-- Physical descriptions begin -->
155156
<layout>
156-
<device_layout name="unnamed_device" width="17" height="17">
157+
<fixed_layout name="unnamed_device" width="17" height="17">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
158159
<perimeter type="io" priority="100"/>
159160
<corners type="EMPTY" priority="101"/>
@@ -165,7 +166,7 @@ Each 2-to-1 mux adds 6 MWTAs for SRAM cell.
165166
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
166167
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
167168
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
168-
</device_layout>
169+
</fixed_layout>
169170
</layout>
170171
<device>
171172
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_frac_2uripple_N8_22nm.xml

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
112112
</fc>
113113
<pinlocations pattern="custom">
114114
<loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
115-
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
115+
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
116+
<loc side="top">clb.cin</loc>
116117
</pinlocations>
117118
</sub_tile>
118119
</tile>
@@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
148149
<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
150151
<layout>
151-
<device_layout name="unnamed_device" width="17" height="17">
152+
<fixed_layout name="unnamed_device" width="17" height="17">
152153
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
153154
<perimeter type="io" priority="100"/>
154155
<corners type="EMPTY" priority="101"/>
@@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
160161
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
161162
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
162163
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
163-
</device_layout>
164+
</fixed_layout>
164165
</layout>
165166
<device>
166167
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_frac_N8_22nm.xml

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
134134
<layout>
135-
<device_layout name="unnamed_device" width="17" height="17">
135+
<fixed_layout name="unnamed_device" width="17" height="17">
136136
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
137137
<perimeter type="io" priority="100"/>
138138
<corners type="EMPTY" priority="101"/>
@@ -144,7 +144,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
144144
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
145145
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
146146
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
147-
</device_layout>
147+
</fixed_layout>
148148
</layout>
149149
<device>
150150
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_frac_ripple_N8_22nm.xml

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
112112
</fc>
113113
<pinlocations pattern="custom">
114114
<loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
115-
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
115+
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
116+
<loc side="top">clb.cin</loc>
116117
</pinlocations>
117118
</sub_tile>
118119
</tile>
@@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
148149
<!-- ODIN II specific config ends -->
149150
<!-- Physical descriptions begin -->
150151
<layout>
151-
<device_layout name="unnamed_device" width="17" height="17">
152+
<fixed_layout name="unnamed_device" width="17" height="17">
152153
<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
153154
<perimeter type="io" priority="100"/>
154155
<corners type="EMPTY" priority="101"/>
@@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
160161
<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
161162
<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
162163
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
163-
</device_layout>
164+
</fixed_layout>
164165
</layout>
165166
<device>
166167
<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

‎vtr_flow/arch/timing/fixed_size/fixed_k6_frac_uripple_N8_22nm.xml

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,8 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
112112
</fc>
113113
<pinlocations pattern="custom">
114114
<loc side="right">clb.O clb.I1[4:0] clb.I2[4:0] clb.I3[4:0] clb.I4[4:0] clb.clk</loc>
115-
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5]</loc>
115+
<loc side="bottom">clb.O clb.I1[9:5] clb.I2[9:5] clb.I3[9:5] clb.I4[9:5] clb.cout</loc>
116+
<loc side="top">clb.cin</loc>
116117
</pinlocations>
117118
</sub_tile>
118119
</tile>
@@ -148,7 +149,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout>
151-
<device_layout name="unnamed_device" width="17" height="17">
152+
<fixed_layout name="unnamed_device" width="17" height="17">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
@@ -160,7 +161,7 @@ Scaling assumptions from 40nm to 22nm: delay constant area drop (22/40)^2 but si
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<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
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<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
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<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
163-
</device_layout>
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</fixed_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="13090.000000" R_minW_pmos="19086.831111"/>

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