[Infra]: - add blockbox attribute to SPRAM/DPRAM

	 - remove arm_core reg init values
	 - modify synthesis.ys to perform formal synthesis

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

vtr_flow/benchmarks/verilog/arm_core.v

@@ -20,7 +20,7 @@
        reg looping; 
 
 assign temp = u_var * DXport;
-    always @(posedge clk)
+    always @(posedge clk or posedge reset)
     begin
 		if (reset == 1'b1)
 		begin

vtr_flow/benchmarks/verilog/diffeq1.v

@@ -194,8 +194,8 @@ endmodule  // Max
 
 
 
-// SimpleDualPortRAM_generic : 4 RAM banks ( = no. of actions) with a depth of 12 ( = no. of states). Writes during training. Reads during inferfence.
-module SimpleDualPortRAM_generic
+// Simpledual_port_ram_generic : 4 RAM banks ( = no. of actions) with a depth of 12 ( = no. of states). Writes during training. Reads during inferfence.
+module Simpledual_port_ram_generic
           (clk,
            enb,
            wr_din,
@@ -275,7 +275,7 @@ dual_port_ram u_dual_port_ram(
 
 assign rd_dout = data_int;
 
-endmodule  // SimpleDualPortRAM_generic
+endmodule  // Simpledual_port_ram_generic
 
 // Q_Hw: connects all the blocks and incorporates pipelining for appropriate syncing. 
 module Q_HW
@@ -545,7 +545,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
              .out0(Max_out1),  // int16
              .clk(clk));
 
-  SimpleDualPortRAM_generic #(.AddrWidth(4),
+  Simpledual_port_ram_generic #(.AddrWidth(4),
                               .DataWidth(32)
                               )
                             u_Simple_Dual_Port_RAM_System_bank3 (.clk(clk),
@@ -557,7 +557,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
                                                                  .rd_dout(pre_rd_out)
                                                                  );
 
-  SimpleDualPortRAM_generic #(.AddrWidth(4),
+  Simpledual_port_ram_generic #(.AddrWidth(4),
                               .DataWidth(32)
                               )
                             u_Simple_Dual_Port_RAM_System_bank2 (.clk(clk),
@@ -569,7 +569,7 @@ assign Data_Type_Conversion_out1_3 = Data_Type_Conversion_out1_3;
                                                                  .rd_dout(pre_rd_out_1)
                                                                  );
 
-  SimpleDualPortRAM_generic #(.AddrWidth(4),
+  Simpledual_port_ram_generic #(.AddrWidth(4),
                               .DataWidth(32)
                               )
                             u_Simple_Dual_Port_RAM_System_bank1 (.clk(clk),

vtr_flow/benchmarks/verilog/koios/robot_rl.v

@@ -18329,7 +18329,7 @@ single_port_ram sinp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1
 
 defparam cosp_replace.ADDR_WIDTH = 10;
 defparam cosp_replace.DATA_WIDTH = 32;
-single_port_ram cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp));
+singlePortRam cosp_replace(.clk (clock), .addr (pindex), .data (blank), .we (1'b0), .out (cosp));
 
 
 endmodule

vtr_flow/benchmarks/verilog/mcml.v

@@ -1,68 +1,79 @@
-# XXX is replaced with filename by run_vtr_flow.pl
+# XXX is replaced with filename by the run_vtr_flow script
 read_verilog -nolatches XXX
 
 # These commands follow the generic `synth'
 # command script inside Yosys
 # The -libdir argument allows Yosys to search the current 
 # directory for any definitions to modules it doesn't know
 # about, such as hand-instantiated (not inferred) memories
-hierarchy -check -auto-top -libdir . -libdir TTT
+hierarchy -check -auto-top -libdir .
 proc
 
 # Check that there are no combinational loops
 scc -select
 select -assert-none %
 select -clear
 
+
+opt_expr
+opt_clean
+check
+opt -nodffe -nosdff
+fsm
 opt
 wreduce
-# Do not transform $add/$mul ops to $alu and $macc cells
-#alumacc
+peepopt
+opt_clean
 share
 opt
-fsm
-opt -fast
 memory -nomap
-opt_clean
-# But instead of using the `memory_map' command, 
-# we map any memories, multipliers, and adders into 
-# VTR primitives (e.g. single_port_ram)
 opt -full
 
 # Transform all async FFs into synchronous ones
 techmap -map +/adff2dff.v
+techmap -map TTT/../../../ODIN_II/techlib/adffe2dff.v
+
 # Map multipliers, DSPs, and add/subtracts according to yosys_models.v
 techmap -map YYY */t:$mul */t:$mem */t:$sub */t:$add
+opt -fast -full
+
 memory_map
 # Taking care to remove any undefined muxes that
 # are introduced to promote resource sharing
 opt -full
+
 # Then techmap all other `complex' blocks into basic
 # (lookup table) logic
 techmap 
 opt -fast
 
 flatten
-# Perform technology-mapping using ABC
-techmap -map YYY */t:$lut 
-opt -fast
-
 # Turn all DFFs into simple latches
 dffunmap
+opt -fast -noff
 
 # We read the definitions for all the VTR primitives
 # as blackboxes
 read_verilog -lib TTT/adder.v
 read_verilog -lib TTT/multiply.v
-read_verilog -lib -ignore_redef TTT/single_port_ram.v
-read_verilog -lib -ignore_redef TTT/dual_port_ram.v
+read_verilog -lib SSS     #(SSS) will be replaced by single_port_ram.v by python script
+read_verilog -lib DDD     #(DDD) will be replaced by dual_port_ram.v by python script
+
+# Rename singlePortRam to single_port_ram
+# Rename dualPortRam to dualZ_port_ram
+# rename function of Yosys not work here
+# since it may outcome hierarchy error
+read_verilog SSR         #(SSR) will be replaced by spram_rename.v by python script
+read_verilog DDR         #(DDR) will be replaced by dpram_rename.v by python script
+
 
 # Lastly, check the hierarchy for any unknown modules,
 # and purge all modules (including blackboxes) that
 # aren't used
 hierarchy -check -purge_lib
 tee -o /dev/stdout stat
 
+
 # Then write it out as a blif file, remembering to call
 # the internal `$true'/`$false' signals vcc/gnd, but
 # switch `-impltf' doesn't output them

vtr_flow/misc/synthesis.ys

@@ -0,0 +1,60 @@
+`timescale 1ps/1ps
+
+`define MEM_MAXADDR PPP
+`define MEM_MAXDATA 36
+
+// depth and data may need to be splited
+module dualPortRam(clk, we1, we2, addr1, addr2, data1, data2, out1, out2);
+    parameter ADDR_WIDTH = 1;
+    parameter DATA_WIDTH = 1;
+
+    input clk;
+    input we1, we2;
+    input [ADDR_WIDTH-1:0] addr1, addr2;
+    input [DATA_WIDTH-1:0] data1, data2;
+
+    output reg [DATA_WIDTH-1:0] out1, out2;
+
+
+    dual_port_ram uut (
+        .clk(clk), 
+        .we1(we1), 
+        .we2(we2), 
+        .addr1(addr1), 
+        .addr2(addr2), 
+        .data1(data1), 
+        .data2(data2), 
+        .out1(out1),
+        .out2(out2)
+    );
+    
+endmodule
+
+
+
+(* blackbox *)
+module dual_port_ram(clk, data2, data1, addr2, addr1, we2, we1, out2, out1);
+    localparam ADDR_WIDTH = `MEM_MAXADDR;
+    localparam DATA_WIDTH = 1;
+
+    input clk;
+    input we1, we2;
+    input [ADDR_WIDTH-1:0] addr1, addr2;
+    input data1, data2;
+
+    output reg out1, out2;
+    /*
+    reg [DATA_WIDTH-1:0] RAM [(1<<ADDR_WIDTH)-1:0];
+
+    always @(posedge clk)
+    begin
+        if (we1)
+                RAM[addr1] <= data1;
+        if (we2)
+                RAM[addr2] <= data2;
+                
+        out1 <= RAM[addr1];
+        out2 <= RAM[addr2];
+    end
+    */
+endmodule

vtr_flow/misc/yosyslib/dpram_rename.v

@@ -0,0 +1,110 @@
+`timescale 1ps/1ps
+
+`define MEM_MAXADDR PPP
+`define MEM_MAXDATA 36
+
+// depth and data may need to be splited
+module dualPortRam(clk, we1, we2, addr1, addr2, data1, data2, out1, out2);
+    parameter ADDR_WIDTH = 1;
+    parameter DATA_WIDTH = 1;
+
+    input clk;
+    input we1, we2;
+    input [ADDR_WIDTH-1:0] addr1, addr2;
+    input [DATA_WIDTH-1:0] data1, data2;
+
+    output reg [DATA_WIDTH-1:0] out1, out2;
+
+    genvar i;
+	generate 
+		// split in depth
+		if (ADDR_WIDTH > `MEM_MAXADDR)
+		begin
+			
+            wire [ADDR_WIDTH-2:0] new_addr1 = addr1[ADDR_WIDTH-2:0];
+            wire [ADDR_WIDTH-2:0] new_addr2 = addr2[ADDR_WIDTH-2:0];
+
+            wire [DATA_WIDTH-1:0] out1_h, out1_l;
+            wire [DATA_WIDTH-1:0] out2_h, out2_l;
+
+
+            defparam uut_h.ADDR_WIDTH = ADDR_WIDTH-1;
+            defparam uut_h.DATA_WIDTH = DATA_WIDTH;
+            dualPortRam uut_h (
+                .clk(clk), 
+                .we1(we1), 
+                .we2(we2), 
+                .addr1(new_addr1), 
+                .addr2(new_addr2), 
+                .data1(data1), 
+                .data2(data2), 
+                .out1(out1_h),
+                .out2(out2_h)
+            );
+
+            defparam uut_l.ADDR_WIDTH = ADDR_WIDTH-1;
+            defparam uut_l.DATA_WIDTH = DATA_WIDTH;
+            dualPortRam uut_l (
+                .clk(clk), 
+                .we1(we1), 
+                .we2(we2), 
+                .addr1(new_addr1), 
+                .addr2(new_addr2), 
+                .data1(data1), 
+                .data2(data2), 
+                .out1(out1_l),
+                .out2(out2_l)
+            );
+
+            reg additional_bit;
+            always @(posedge clk) additional_bit <= addr[ADDR_WIDTH-1];
+            assign out1 = (additional_bit) ? out1_h : out1_l;
+            assign out2 = (additional_bit) ? out2_h : out2_l;
+
+        end	else begin
+            for (i = 0; i < DATA_WIDTH; i = i + 1) begin:single_bit_data
+                dual_port_ram uut (
+                    .clk(clk), 
+                    .we1(we1), 
+                    .we2(we2), 
+                    .addr1(addr1), 
+                    .addr2(addr2), 
+                    .data1(data1[i]), 
+                    .data2(data2[i]), 
+                    .out1(out1[i]),
+                    .out2(out2[i])
+                );
+            end
+        end
+    endgenerate
+    
+endmodule
+
+
+
+(* blackbox *)
+module dual_port_ram(clk, data2, data1, addr2, addr1, we2, we1, out2, out1);
+    localparam ADDR_WIDTH = `MEM_MAXADDR;
+    localparam DATA_WIDTH = 1;
+
+    input clk;
+    input we1, we2;
+    input [ADDR_WIDTH-1:0] addr1, addr2;
+    input data1, data2;
+
+    output reg out1, out2;
+    /*
+    reg [DATA_WIDTH-1:0] RAM [(1<<ADDR_WIDTH)-1:0];
+
+    always @(posedge clk)
+    begin
+        if (we1)
+                RAM[addr1] <= data1;
+        if (we2)
+                RAM[addr2] <= data2;
+                
+        out1 <= RAM[addr1];
+        out2 <= RAM[addr2];
+    end
+    */
+endmodule