[Infra]: - remove constant output drivers in mcml

	 - fix multiple conflicting drivers error in boundtop

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

ODIN_II/regression_test/benchmark/verilog/full/mcml.v

@@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;	
@@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 36'b000000000000000000000000000000000000;
-assign dont_care_out = 36'b000000000000000000000000000000000000;
+// assign dont_care_out = 36'b000000000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 36;
@@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 18'b000000000000000000;
-assign dont_care_out = 18'b000000000000000000;
+// assign dont_care_out = 18'b000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 18;
@@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 8'b00000000;
-assign dont_care_out = 8'b00000000;
+// assign dont_care_out = 8'b00000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 8;

vtr_flow/benchmarks/verilog/boundtop.v

@@ -222,7 +222,7 @@ wire[63:0] tldata;
         resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); 
         rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); 
         boundcontroller  boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01);
-        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01);
+        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10);
         resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); 
 
 assign raygroupout = raygroupout01 | raygroupout10 ;

vtr_flow/benchmarks/verilog/mcml.v

@@ -1776,7 +1776,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;	
@@ -1813,7 +1813,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1850,7 +1850,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1887,7 +1887,7 @@ wire [31:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 32'b00000000000000000000000000000000;
-assign dont_care_out = 32'b00000000000000000000000000000000;
+// assign dont_care_out = 32'b00000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 13;
 defparam dpram1.DATA_WIDTH = 32;
@@ -1923,7 +1923,7 @@ wire [35:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 36'b000000000000000000000000000000000000;
-assign dont_care_out = 36'b000000000000000000000000000000000000;
+// assign dont_care_out = 36'b000000000000000000000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 36;
@@ -1959,7 +1959,7 @@ wire [17:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 18'b000000000000000000;
-assign dont_care_out = 18'b000000000000000000;
+// assign dont_care_out = 18'b000000000000000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 18;
@@ -1995,7 +1995,7 @@ wire [7:0] dont_care_out;
 
 assign const_zero = 1'b0;
 assign const_zero_data = 8'b00000000;
-assign dont_care_out = 8'b00000000;
+// assign dont_care_out = 8'b00000000;
 
 defparam dpram1.ADDR_WIDTH = 16;
 defparam dpram1.DATA_WIDTH = 8;