[Infra]: - add Yosys synthesizer to the VTR flow

	 - add yosys stage to run_vtr_flow script.
	 - add yosyslib and vtr primitive verilog files to vtr_flow/misc
	 - add slightly modified VTR compatible yosys_models adapted from @eddiehung version
	 - add vtr_reg_yosys running VTR benchmarks using Yosys as the VTR front-end
	 - modify CMakeList to add the libyosys to the VTR build tree

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

CMakeLists.txt

@@ -52,6 +52,7 @@ option(ODIN_TIDY "Enable building odin with clang tidy" OFF)
 option(ODIN_SANITIZE "Enable building odin with sanitize flags" OFF)
 
 # Allow the user to enable building Yosys
+option(WITH_YOSYS "Enable building Yosys" OFF)
 option(ODIN_USE_YOSYS "Enable building Yosys" OFF)
 
 set(VTR_VERSION_MAJOR 8)
@@ -381,14 +382,18 @@ if(${WITH_ABC})
     add_subdirectory(ace2)
 endif()
 add_subdirectory(utils)
-if(${WITH_ODIN})
+# define cmake params to compile Yosys
+if(${WITH_YOSYS})
+    add_definitions("-D_YOSYS_")
+elseif(${WITH_ODIN})
     add_subdirectory(ODIN_II)
     # blifexplorer depends on odin
     if(${WITH_BLIFEXPLORER})
         add_subdirectory(blifexplorer)
     endif()
 endif()
 
+
 #Add extra compilation flags to suppress warnings from some libraries/tools
 # Note that target_compile_options() *appends* to the current compilation options of
 # the specified target

libs/EXTERNAL/CMakeLists.txt

@@ -14,9 +14,9 @@ if(VPR_USE_EZGL STREQUAL "on")
     add_subdirectory(libezgl)
 endif()
 
-# The VTR root CMakeFile initializes the ODIN_USE_YOSYS
+# The VTR root CMakeFile initializes the ODIN_USE_YOSYS or WITH_YOSYS
 # Yosys is compiled only if the user ask for it
-if(${ODIN_USE_YOSYS})
+if(${ODIN_USE_YOSYS} OR ${WITH_YOSYS})
     add_subdirectory(libyosys)
 endif()
 

libs/EXTERNAL/libyosys/CMakeLists.txt

@@ -1,42 +1,41 @@
 cmake_minimum_required(VERSION 3.9)
 
-# [KNOWN_ISSUE]: if ODIN_USE_YOSYS is active, abc will be compiled 
-# for the second time inside Yosys, since Yosys uses a different
-# version of abc
 project("libyosys")
 
 # Create a target out of the library compilation result
 SET(LIB_FILE ${CMAKE_CURRENT_SOURCE_DIR}/libyosys.so)
 SET(BINARY_LIB_FILE ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/libyosys.so)
+SET(YOSYS_EXEC ${CMAKE_CURRENT_SOURCE_DIR}/yosys)
+SET(BINARY_EXEC_FILE ${CMAKE_CURRENT_BINARY_DIR}/bin/yosys)
 SET(YOSYS_INCLUDE_DIRS ${CMAKE_CURRENT_SOURCE_DIR})
 
 # handle make program with both ninja and unix style
 set(MAKE_PROGRAM "$(MAKE)")
 # handle cppflags to suppress yosys warning with both ninja and unix style
 set(CURRENT_CPPFLAGS "$(CPPFLAGS)-w")
 if(${CMAKE_GENERATOR} STREQUAL "Ninja")
-    set(MAKE_PROGRAM "make")
-    set(CURRENT_CPPFLAGS "-w")
+set(MAKE_PROGRAM "make")
+set(CURRENT_CPPFLAGS "-w")
 endif()
 
 # how to build the result of the library
-add_custom_command(OUTPUT  ${LIB_FILE} ${BINARY_LIB_FILE}
-                   COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1" 
-                                           CPPFLAGS=${CURRENT_CPPFLAGS}
-                                           -j${CMAKE_BUILD_PARALLEL_LEVEL}
-                                           PREFIX=${CMAKE_CURRENT_BINARY_DIR}
-                                           > /dev/null
-                   COMMAND ${MAKE_PROGRAM} install 
-                                           PREFIX=${CMAKE_CURRENT_BINARY_DIR}
-                                           > /dev/null
-                   COMMAND ${CMAKE_COMMAND} -E 
-                                           make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
-                   COMMAND ${CMAKE_COMMAND} -E 
-                                           copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
-                   WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
+add_custom_command(OUTPUT  ${LIB_FILE} ${BINARY_LIB_FILE} ${YOSYS_EXEC} ${BINARY_EXEC_FILE}
+                COMMAND ${MAKE_PROGRAM} -k "ENABLE_LIBYOSYS=1" "ENABLE_ABC=0"
+                                        CPPFLAGS=${CURRENT_CPPFLAGS}
+                                        -j${CMAKE_BUILD_PARALLEL_LEVEL}
+                                        PREFIX=${CMAKE_CURRENT_BINARY_DIR}
+                                        > /dev/null
+                COMMAND ${MAKE_PROGRAM} install 
+                                        PREFIX=${CMAKE_CURRENT_BINARY_DIR}
+                                        > /dev/null
+                COMMAND ${CMAKE_COMMAND} -E 
+                                        make_directory ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
+                COMMAND ${CMAKE_COMMAND} -E 
+                                        copy ${LIB_FILE} ${CMAKE_CURRENT_BINARY_DIR}/lib/yosys/
+                WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
 
 # create a target out of the library compilation result
-add_custom_target(yosys DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE})
+add_custom_target(yosys ALL DEPENDS ${LIB_FILE} ${BINARY_LIB_FILE})
 
 # create an library target out of the library compilation result
 add_library(libyosys SHARED IMPORTED GLOBAL)
@@ -47,3 +46,6 @@ set_target_properties(libyosys
     PROPERTIES PREFIX "" #Avoid extra 'lib' prefix
     IMPORTED_LOCATION ${LIB_FILE}
     INTERFACE_INCLUDE_DIRECTORIES ${YOSYS_INCLUDE_DIRS})
+
+
+install(FILES ${YOSYS_EXEC} DESTINATION ${CMAKE_CURRENT_BINARY_DIR})

vtr_flow/misc/synthesis.ys

@@ -0,0 +1,70 @@
+# XXX is replaced with filename by run_vtr_flow.pl
+read_verilog -nolatches XXX
+
+# These commands follow the generic `synth'
+# command script inside Yosys
+# The -libdir argument allows Yosys to search the current 
+# directory for any definitions to modules it doesn't know
+# about, such as hand-instantiated (not inferred) memories
+hierarchy -check -auto-top -libdir . -libdir TTT
+proc
+
+# Check that there are no combinational loops
+scc -select
+select -assert-none %
+select -clear
+
+opt
+wreduce
+# Do not transform $add/$mul ops to $alu and $macc cells
+#alumacc
+share
+opt
+fsm
+opt -fast
+memory -nomap
+opt_clean
+# But instead of using the `memory_map' command, 
+# we map any memories, multipliers, and adders into 
+# VTR primitives (e.g. single_port_ram)
+opt -full
+
+# Transform all async FFs into synchronous ones
+techmap -map +/adff2dff.v
+# Map multipliers, DSPs, and add/subtracts according to yosys_models.v
+techmap -map YYY */t:$mul */t:$mem */t:$sub */t:$add
+memory_map
+# Taking care to remove any undefined muxes that
+# are introduced to promote resource sharing
+opt -full
+# Then techmap all other `complex' blocks into basic
+# (lookup table) logic
+techmap 
+opt -fast
+
+flatten
+# Perform technology-mapping using ABC
+techmap -map YYY */t:$lut 
+opt -fast
+
+# Turn all DFFs into simple latches
+dffunmap
+
+# We read the definitions for all the VTR primitives
+# as blackboxes
+read_verilog -lib TTT/adder.v
+read_verilog -lib TTT/multiply.v
+read_verilog -lib -ignore_redef TTT/single_port_ram.v
+read_verilog -lib -ignore_redef TTT/dual_port_ram.v
+
+# Lastly, check the hierarchy for any unknown modules,
+# and purge all modules (including blackboxes) that
+# aren't used
+hierarchy -check -purge_lib
+tee -o /dev/stdout stat
+
+# Then write it out as a blif file, remembering to call
+# the internal `$true'/`$false' signals vcc/gnd, but
+# switch `-impltf' doesn't output them
+# ZZZ will be replaced by run_vtr_flow.pl
+write_blif -true - vcc -false - gnd -undef - unconn -blackbox ZZZ

vtr_flow/misc/yosyslib/adder.v

@@ -0,0 +1,7 @@
+(* blackbox *)
+module adder(a, b, cin, cout, sumout);
+	input a, b, cin;
+	output cout, sumout;
+	
+	//assign {cout,sumout} = a + b + cin;
+endmodule

vtr_flow/misc/yosyslib/dual_port_ram.v

@@ -0,0 +1,25 @@
+`timescale 1ps/1ps
+
+module dual_port_ram(clk, we1, we2, addr1, addr2, data1, data2, out1, out2);
+    parameter ADDR_WIDTH = 15;
+    parameter DATA_WIDTH = 1;
+
+    input clk;
+    input we1, we2;
+    input [ADDR_WIDTH-1:0] addr1, addr2;
+    input [DATA_WIDTH-1:0] data1, data2;
+
+    output reg [DATA_WIDTH-1:0] out1, out2;
+    reg [DATA_WIDTH-1:0] RAM [(1<<ADDR_WIDTH)-1:0];
+
+    always @(posedge clk)
+    begin
+        if (we1)
+                RAM[addr1] <= data1;
+        if (we2)
+                RAM[addr2] <= data2;
+                
+        out1 <= RAM[addr1];
+        out2 <= RAM[addr2];
+    end
+endmodule

vtr_flow/misc/yosyslib/multiply.v

@@ -0,0 +1,13 @@
+(* blackbox *)
+module multiply(a, b, out);
+	parameter A_WIDTH = 36;
+	parameter B_WIDTH = 36;
+	parameter Y_WIDTH = A_WIDTH+B_WIDTH;
+	
+	input [A_WIDTH-1:0] a;
+	input [B_WIDTH-1:0] b;
+	output [Y_WIDTH-1:0] out;
+
+	//assign out = a * b;
+	
+endmodule

vtr_flow/misc/yosyslib/single_port_ram.v

@@ -0,0 +1,23 @@
+`timescale 1ps/1ps
+
+module single_port_ram(clk, we, addr, data, out);
+
+    parameter ADDR_WIDTH = 15;
+    parameter DATA_WIDTH = 1;
+
+    input clk;
+    input we;
+    input [ADDR_WIDTH-1:0] addr;
+    input [DATA_WIDTH-1:0] data;
+    
+    output reg [DATA_WIDTH-1:0] out;
+    reg [DATA_WIDTH-1:0] RAM [(1<<ADDR_WIDTH)-1:0];
+
+    always @(posedge clk)
+    begin
+        if (we)
+                RAM[addr] <= data;
+                
+        out <= RAM[addr];
+    end
+endmodule