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sdamghansdamghan
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Merge pull request #2013 from sdamghan/yosys_odin_mul_out
Handle Multiplication Operation Output Size
2 parents 0ea750c + d09ba2c commit a261056

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8 files changed

+56
-83
lines changed

8 files changed

+56
-83
lines changed

‎ODIN_II/SRC/BLIFElaborate.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -485,7 +485,7 @@ static void resolve_arithmetic_nodes(nnode_t* node, uintptr_t traverse_mark_numb
485485
if (!hard_multipliers)
486486
check_constant_multipication(node, traverse_mark_number, netlist);
487487
else
488-
check_multiplier_port_size(node);
488+
check_multiplier_port_size(node, netlist);
489489

490490
/* Adding to mult_list for future checking on hard blocks */
491491
mult_list = insert_in_vptr_list(mult_list, node);

‎ODIN_II/SRC/include/multipliers.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -56,7 +56,7 @@ extern void define_mult_function(nnode_t* node, FILE* out);
5656
extern void split_multiplier(nnode_t* node, int a0, int b0, int a1, int b1, netlist_t* netlist);
5757
extern void iterate_multipliers(netlist_t* netlist);
5858
extern bool check_constant_multipication(nnode_t* node, uintptr_t traverse_mark_number, netlist_t* netlist);
59-
extern void check_multiplier_port_size(nnode_t* node);
59+
extern void check_multiplier_port_size(nnode_t* node, netlist_t* netlist);
6060
extern bool is_ast_multiplier(ast_node_t* node);
6161
extern void clean_multipliers();
6262
extern void free_multipliers();

‎ODIN_II/SRC/multipliers.cpp

Lines changed: 23 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -1765,68 +1765,41 @@ bool is_ast_multiplier(ast_node_t* node) {
17651765
* -------------------------------------------------------------------------
17661766
* (function: check_multiplier_port_size)
17671767
*
1768-
* If output size is less than the max of input sizes, the inputs should
1769-
* be pruned since the most significant bits are useless
1768+
* If output size is less than the sum of input sizes,
1769+
* we need to expand output pins with pad pins
17701770
*
1771-
* @param node pointer to the multiplication node
1771+
* @param node pointer to the multiplication node
1772+
* @param netlist pointer to the current netlist file
17721773
* -----------------------------------------------------------------------
17731774
*/
1774-
void check_multiplier_port_size(nnode_t* node) {
1775+
void check_multiplier_port_size(nnode_t* node, netlist_t* netlist) {
17751776
/* Can only perform the optimisation if hard multipliers exist! */
17761777
if (hard_multipliers == NULL)
17771778
return;
17781779

17791780
int mula = node->input_port_sizes[0];
17801781
int mulb = node->input_port_sizes[1];
1781-
int max = std::max(mula, mulb);
1782+
int sizeout = node->num_output_pins;
1783+
int limit = mula + mulb;
17821784

17831785
/* check the output port size */
1784-
if (node->num_output_pins < max) {
1785-
int limit = node->num_output_pins;
1786-
int new_mula = (mula > limit) ? limit : mula;
1787-
int new_mulb = (mulb > limit) ? limit : mulb;
1788-
npin_t** new_input_pins = (npin_t**)vtr::calloc(new_mula + new_mulb, sizeof(npin_t*));
1789-
1790-
/* handle mula */
1791-
for (int i = 0; i < mula; i++) {
1792-
npin_t* input_pin = node->input_pins[i];
1793-
/* detach from mul node */
1794-
node->input_pins[i] = NULL;
1795-
1796-
if (i < new_mula) {
1797-
new_input_pins[i] = input_pin;
1798-
} else {
1799-
/* detach from its net */
1800-
remove_fanout_pins_from_net(input_pin->net, input_pin, input_pin->pin_net_idx);
1801-
/* free the pin */
1802-
input_pin->node = NULL;
1803-
free_npin(input_pin);
1804-
}
1805-
}
1806-
1807-
/* handle mulb */
1808-
for (int i = 0; i < mulb; i++) {
1809-
npin_t* input_pin = node->input_pins[node->input_port_sizes[0] + i];
1810-
/* detach from mul node */
1811-
node->input_pins[node->input_port_sizes[0] + i] = NULL;
1812-
1813-
if (i < new_mulb) {
1814-
new_input_pins[new_mula + i] = input_pin;
1815-
} else {
1816-
/* detach from its net */
1817-
remove_fanout_pins_from_net(input_pin->net, input_pin, input_pin->pin_net_idx);
1818-
/* free the pin */
1819-
input_pin->node = NULL;
1820-
free_npin(input_pin);
1821-
}
1786+
if (node->num_output_pins < limit) {
1787+
// Set the limit value as the number of output pins
1788+
node->num_output_pins = limit;
1789+
node->output_port_sizes[0] = limit;
1790+
// Keep record of old output pins pointer for cleaning up later
1791+
npin_t** old_output_pins = node->output_pins;
1792+
node->output_pins = (npin_t**)calloc(node->num_output_pins, sizeof(npin_t*));
1793+
1794+
// Move output pins to new array and adding pad pins in extra spots
1795+
for (int i = 0; i < node->num_output_pins; i++) {
1796+
if (i < sizeout)
1797+
node->output_pins[i] = old_output_pins[i];
1798+
else
1799+
add_output_pin_to_node(node, get_pad_pin(netlist), i);
18221800
}
1823-
1824-
/* free old input pin list */
1825-
vtr::free(node->input_pins);
1826-
node->input_pins = new_input_pins;
1827-
node->num_input_pins = new_mula + new_mulb;
1828-
node->input_port_sizes[0] = new_mula;
1829-
node->input_port_sizes[1] = new_mulb;
1801+
// CLEAN UP
1802+
vtr::free(old_output_pins);
18301803
}
18311804
}
18321805
/*-------------------------------------------------------------------------

‎ODIN_II/regression_test/benchmark/task/yosys+odin/koios/synthesis_result.json

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -4838,16 +4838,16 @@
48384838
"Latch Drivers": 1,
48394839
"Pi": 2,
48404840
"Po": 384,
4841-
"logic element": 7498,
4842-
"latch": 1876,
4843-
"Adder": 1188,
4841+
"logic element": 9718,
4842+
"latch": 2596,
4843+
"Adder": 1788,
48444844
"Multiplier": 24,
48454845
"Memory": 48,
48464846
"generic logic size": 4,
4847-
"Longest Path": 129,
4847+
"Longest Path": 139,
48484848
"Average Path": 4,
4849-
"Estimated LUTs": 7718,
4850-
"Total Node": 10635
4849+
"Estimated LUTs": 9938,
4850+
"Total Node": 14175
48514851
},
48524852
"koios/softmax/k6FracN10LB_mem20K_complexDSP_customSB_22nm": {
48534853
"test_name": "koios/softmax/k6FracN10LB_mem20K_complexDSP_customSB_22nm",

‎ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -371,15 +371,15 @@
371371
"Latch Drivers": 1,
372372
"Pi": 235,
373373
"Po": 305,
374-
"logic element": 2927,
375-
"latch": 1019,
376-
"Adder": 411,
374+
"logic element": 2938,
375+
"latch": 1024,
376+
"Adder": 413,
377377
"Multiplier": 15,
378378
"generic logic size": 4,
379379
"Longest Path": 110,
380380
"Average Path": 4,
381-
"Estimated LUTs": 2984,
382-
"Total Node": 4373
381+
"Estimated LUTs": 2995,
382+
"Total Node": 4391
383383
},
384384
"large/paj_top_hierarchy_no_mem/k6_frac_N10_frac_chain_mem32K_40nm": {
385385
"test_name": "large/paj_top_hierarchy_no_mem/k6_frac_N10_frac_chain_mem32K_40nm",
@@ -409,16 +409,16 @@
409409
"Latch Drivers": 1,
410410
"Pi": 235,
411411
"Po": 305,
412-
"logic element": 2705,
413-
"latch": 1027,
414-
"Adder": 411,
412+
"logic element": 2716,
413+
"latch": 1032,
414+
"Adder": 413,
415415
"Multiplier": 15,
416416
"Memory": 21,
417417
"generic logic size": 4,
418418
"Longest Path": 111,
419419
"Average Path": 4,
420-
"Estimated LUTs": 2764,
421-
"Total Node": 4180
420+
"Estimated LUTs": 2775,
421+
"Total Node": 4198
422422
},
423423
"large/spree/k6_frac_N10_frac_chain_mem32K_40nm": {
424424
"test_name": "large/spree/k6_frac_N10_frac_chain_mem32K_40nm",
@@ -433,16 +433,16 @@
433433
"Latch Drivers": 1,
434434
"Pi": 44,
435435
"Po": 32,
436-
"logic element": 2640,
436+
"logic element": 2656,
437437
"latch": 224,
438438
"Adder": 62,
439439
"Multiplier": 1,
440440
"Memory": 128,
441441
"generic logic size": 4,
442442
"Longest Path": 764,
443443
"Average Path": 3,
444-
"Estimated LUTs": 2904,
445-
"Total Node": 3056
444+
"Estimated LUTs": 2920,
445+
"Total Node": 3072
446446
},
447447
"large/sv_chip0_hierarchy_no_mem/k6_frac_N10_frac_chain_mem32K_40nm": {
448448
"test_name": "large/sv_chip0_hierarchy_no_mem/k6_frac_N10_frac_chain_mem32K_40nm",

‎ODIN_II/regression_test/benchmark/task/yosys+odin/micro/simulation_result.json

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -208,7 +208,7 @@
208208
"simulation_time(ms)": 2335.8,
209209
"test_coverage(%)": 100,
210210
"Latch Drivers": 1,
211-
"Pi": 528,
211+
"Pi": 608,
212212
"Po": 144,
213213
"logic element": 232,
214214
"latch": 144,
@@ -248,7 +248,7 @@
248248
"simulation_time(ms)": 2281.1,
249249
"test_coverage(%)": 100,
250250
"Latch Drivers": 1,
251-
"Pi": 528,
251+
"Pi": 608,
252252
"Po": 144,
253253
"logic element": 496,
254254
"latch": 144,

‎ODIN_II/regression_test/benchmark/task/yosys+odin/micro/synthesis_result.json

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -230,7 +230,7 @@
230230
"techmap_time(ms)": 4.3,
231231
"synthesis_time(ms)": 234,
232232
"Latch Drivers": 1,
233-
"Pi": 528,
233+
"Pi": 608,
234234
"Po": 144,
235235
"logic element": 88,
236236
"latch": 144,
@@ -274,7 +274,7 @@
274274
"techmap_time(ms)": 7.3,
275275
"synthesis_time(ms)": 214,
276276
"Latch Drivers": 1,
277-
"Pi": 528,
277+
"Pi": 608,
278278
"Po": 144,
279279
"logic element": 352,
280280
"latch": 144,

‎ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -446,16 +446,16 @@
446446
"Latch Drivers": 1,
447447
"Pi": 235,
448448
"Po": 305,
449-
"logic element": 2705,
450-
"latch": 1027,
451-
"Adder": 411,
449+
"logic element": 2716,
450+
"latch": 1032,
451+
"Adder": 413,
452452
"Multiplier": 15,
453453
"Memory": 21,
454454
"generic logic size": 4,
455455
"Longest Path": 111,
456456
"Average Path": 4,
457-
"Estimated LUTs": 2764,
458-
"Total Node": 4180
457+
"Estimated LUTs": 2775,
458+
"Total Node": 4198
459459
},
460460
"vtr/sha/k6_frac_N10_frac_chain_mem32K_40nm": {
461461
"test_name": "vtr/sha/k6_frac_N10_frac_chain_mem32K_40nm",
@@ -527,16 +527,16 @@
527527
"Latch Drivers": 1,
528528
"Pi": 44,
529529
"Po": 32,
530-
"logic element": 2640,
530+
"logic element": 2656,
531531
"latch": 224,
532532
"Adder": 62,
533533
"Multiplier": 1,
534534
"Memory": 128,
535535
"generic logic size": 4,
536536
"Longest Path": 764,
537537
"Average Path": 3,
538-
"Estimated LUTs": 2904,
539-
"Total Node": 3056
538+
"Estimated LUTs": 2920,
539+
"Total Node": 3072
540540
},
541541
"vtr/stereovision0/k6_frac_N10_frac_chain_mem32K_40nm": {
542542
"test_name": "vtr/stereovision0/k6_frac_N10_frac_chain_mem32K_40nm",

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