Merge pull request #1784 from verilog-to-routing/documentation_cleanup

Fixing up minor errors within the documentation

Author: vaughnbetz

doc/src/arch/reference.rst

@@ -378,7 +378,7 @@ Grid Location Tags
 
         **Default:** ``0``
 
-    :opt_param incry:
+    :opt_param incrx:
         An expression specifying the horizontal increment between block instantiations within the region.
 
         **Default:** ``w``
@@ -442,7 +442,7 @@ Grid Location Tags
         An expression specifying the vertical repeat factor of the column.
 
     :opt_param incry:
-        An expression specifying the horizontal increment between block instantiations within the region.
+        An expression specifying the vertical increment between block instantiations within the region.
 
         **Default:** ``h``
 
@@ -965,7 +965,7 @@ The following tags are common to all ``<tile>`` tags:
                 Desctibes the mapping of a physical tile's port on the logical block's (pb_type) port.
                 ``direct`` is an option sub-tag of ``site``.
 
-                .. note:: This tag is need only if the pin_mapping of the ``site`` is defined as ``custom``
+                .. note:: This tag is needed only if the pin_mapping of the ``site`` is defined as ``custom``
 
                 Attributes:
                     - ``from`` is relative to the physical tile pins

doc/src/tutorials/arch/fracturable_multiplier_bus.rst

@@ -59,7 +59,7 @@ The mode and slice is declared here:
           <clock name="clk"/>
 
 This is followed by a description of the primitives within the slice.
-There are two sets of 36 flip-flops for the input ports and one set of 64 flip-flops for the output port.
+There are two sets of 36 flip-flops for the input ports and one set of 72 flip-flops for the output port.
 There is one 36x36 multiplier primitive.
 These primitives are described by four *pb_types* as follows: