Skip to content

Commit 93e9758

Browse files
soheilshahrouzsoheilshahrouz
committed
OPIN ---> t_rr_type::OPIN
1 parent 5a118c0 commit 93e9758

File tree

10 files changed

+35
-35
lines changed

10 files changed

+35
-35
lines changed

‎libs/librrgraph/src/base/check_rr_graph.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -156,10 +156,10 @@ void check_rr_graph(const RRGraphView& rr_graph,
156156
*/
157157
bool is_chan_to_chan = (rr_type == CHANX || rr_type == CHANY) && (to_rr_type == CHANY || to_rr_type == CHANX);
158158
bool is_chan_to_ipin = (rr_type == CHANX || rr_type == CHANY) && to_rr_type == t_rr_type::IPIN;
159-
bool is_opin_to_chan = rr_type == OPIN && (to_rr_type == CHANX || to_rr_type == CHANY);
159+
bool is_opin_to_chan = rr_type == t_rr_type::OPIN && (to_rr_type == CHANX || to_rr_type == CHANY);
160160
bool is_internal_edge = false;
161161
if (is_flat) {
162-
is_internal_edge = (rr_type == t_rr_type::IPIN && to_rr_type == t_rr_type::IPIN) || (rr_type == OPIN && to_rr_type == OPIN);
162+
is_internal_edge = (rr_type == t_rr_type::IPIN && to_rr_type == t_rr_type::IPIN) || (rr_type == t_rr_type::OPIN && to_rr_type == t_rr_type::OPIN);
163163
}
164164
if (!(is_chan_to_chan || is_chan_to_ipin || is_opin_to_chan || is_internal_edge)) {
165165
VPR_ERROR(VPR_ERROR_ROUTE,
@@ -169,7 +169,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
169169

170170
//Between two wire segments
171171
VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == t_rr_type::IPIN, "Expect channel type or input pin type");
172-
VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == OPIN, "Expect channel type or output pin type");
172+
VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == t_rr_type::OPIN, "Expect channel type or output pin type");
173173

174174
//While multiple connections between the same wires can be electrically legal,
175175
//they are redundant if they are of the same switch type.
@@ -240,7 +240,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
240240

241241
t_physical_tile_type_ptr type = grid.get_physical_type({xlow, ylow, layer_num});
242242

243-
if (rr_type == t_rr_type::IPIN || rr_type == OPIN) {
243+
if (rr_type == t_rr_type::IPIN || rr_type == t_rr_type::OPIN) {
244244
// #TODO: No edges are added for internal pins. However, they need to be checked somehow!
245245
if (ptc_num >= type->num_pins) {
246246
VTR_LOG_ERROR("in check_rr_graph: node %d (%s) type: %s is internal node.\n",
@@ -273,7 +273,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
273273
|| rr_graph.node_type(rr_node) == CHANY);
274274

275275
if (!is_chain && !is_fringe && !is_wire) {
276-
if (rr_graph.node_type(rr_node) == t_rr_type::IPIN || rr_graph.node_type(rr_node) == OPIN) {
276+
if (rr_graph.node_type(rr_node) == t_rr_type::IPIN || rr_graph.node_type(rr_node) == t_rr_type::OPIN) {
277277
if (has_adjacent_channel(rr_graph, grid, node)) {
278278
auto block_type = grid.get_physical_type({rr_graph.node_xlow(rr_node),
279279
rr_graph.node_ylow(rr_node),
@@ -414,7 +414,7 @@ void check_rr_node(const RRGraphView& rr_graph,
414414
break;
415415
}
416416
case t_rr_type::IPIN:
417-
case OPIN:
417+
case t_rr_type::OPIN:
418418
if (type == nullptr) {
419419
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
420420
"in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow);
@@ -474,11 +474,11 @@ void check_rr_node(const RRGraphView& rr_graph,
474474
}
475475
break;
476476

477-
case OPIN:
477+
case t_rr_type::OPIN:
478478
case t_rr_type::IPIN:
479479
class_type = get_pin_type_from_pin_physical_num(type, ptc_num);
480480
if (ptc_num >= pin_max_ptc
481-
|| class_type != ((rr_type == OPIN) ? DRIVER : RECEIVER)) {
481+
|| class_type != ((rr_type == t_rr_type::OPIN) ? DRIVER : RECEIVER)) {
482482
VPR_ERROR(VPR_ERROR_ROUTE,
483483
"in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num);
484484
}

‎libs/librrgraph/src/base/rr_graph_builder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -48,7 +48,7 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) {
4848
*/
4949
node_lookup_.add_node(node, node_layer, iy, ix, node_type, node_ptc_num, TOTAL_2D_SIDES[0]);
5050
break;
51-
case OPIN:
51+
case t_rr_type::OPIN:
5252
case t_rr_type::IPIN:
5353
for (const e_side& side : TOTAL_2D_SIDES) {
5454
if (node_storage_.is_node_on_specific_side(node, side)) {

‎vpr/src/draw/draw_basic.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -357,7 +357,7 @@ void draw_congestion(ezgl::renderer* g) {
357357
break;
358358

359359
case t_rr_type::IPIN: //fallthrough
360-
case OPIN:
360+
case t_rr_type::OPIN:
361361
draw_rr_pin(inode, color, g);
362362
break;
363363
default:
@@ -651,15 +651,15 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
651651
ezgl::color color = draw_state->draw_rr_node[inode].color;
652652

653653
switch (rr_type) {
654-
case OPIN: {
654+
case t_rr_type::OPIN: {
655655
draw_rr_pin(inode, color, g);
656656
break;
657657
}
658658
case t_rr_type::IPIN: {
659659
draw_rr_pin(inode, color, g);
660660
if (edge_visibility.visible) {
661661
g->set_color(color, edge_visibility.alpha);
662-
if (rr_graph.node_type(prev_node) == OPIN) {
662+
if (rr_graph.node_type(prev_node) == t_rr_type::OPIN) {
663663
draw_pin_to_pin(prev_node, inode, g);
664664
} else {
665665
draw_pin_to_chan_edge(inode, prev_node, g);
@@ -683,7 +683,7 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
683683
draw_chanx_to_chany_edge(inode, prev_node, FROM_Y_TO_X, switch_type, g);
684684
break;
685685
}
686-
case OPIN: {
686+
case t_rr_type::OPIN: {
687687
draw_pin_to_chan_edge(prev_node, inode, g);
688688
break;
689689
}
@@ -716,7 +716,7 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
716716
switch_type, g);
717717
break;
718718
}
719-
case OPIN: {
719+
case t_rr_type::OPIN: {
720720
draw_pin_to_chan_edge(prev_node, inode, g);
721721

722722
break;

‎vpr/src/draw/draw_rr.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@ void draw_rr(ezgl::renderer* g) {
6666
case CHANY:
6767
draw_state->draw_rr_node[inode].color = DEFAULT_RR_NODE_COLOR;
6868
break;
69-
case OPIN:
69+
case t_rr_type::OPIN:
7070
draw_state->draw_rr_node[inode].color = ezgl::PINK;
7171
break;
7272
case t_rr_type::IPIN:
@@ -113,7 +113,7 @@ void draw_rr(ezgl::renderer* g) {
113113
draw_rr_edges(inode, g);
114114
break;
115115

116-
case OPIN:
116+
case t_rr_type::OPIN:
117117
draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g);
118118
draw_rr_edges(inode, g);
119119
break;
@@ -287,7 +287,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
287287
from_type = rr_graph.node_type(rr_node);
288288

289289
if ((draw_state->draw_rr_toggle == DRAW_NODES_RR)
290-
|| (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == OPIN || from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN))
290+
|| (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == t_rr_type::OPIN || from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN))
291291
|| (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN))) {
292292
return; /* Nothing to draw. */
293293
}
@@ -301,7 +301,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
301301
continue; // skip drawing if edge is not valid to draw
302302

303303
switch (from_type) {
304-
case OPIN:
304+
case t_rr_type::OPIN:
305305
switch (to_type) {
306306
case CHANX:
307307
case CHANY:
@@ -494,7 +494,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
494494
break;
495495
case t_rr_type::SOURCE: // from_type
496496
switch (to_type) {
497-
case OPIN:
497+
case t_rr_type::OPIN:
498498
g->set_color(ezgl::PLUM, transparency_factor);
499499
draw_source_to_pin(inode, to_node, g);
500500
break;
@@ -687,7 +687,7 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) {
687687
}
688688
switch (rr_graph.node_type(inode)) {
689689
case t_rr_type::IPIN:
690-
case OPIN: {
690+
case t_rr_type::OPIN: {
691691
int i = rr_graph.node_xlow(inode);
692692
int j = rr_graph.node_ylow(inode);
693693
t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({i, j, layer_num});
@@ -825,7 +825,7 @@ void draw_rr_costs(ezgl::renderer* g, const vtr::vector<RRNodeId, float>& rr_cos
825825
draw_rr_pin(inode, color, g);
826826
if (with_edges) draw_rr_edges(inode, g);
827827
break;
828-
case OPIN:
828+
case t_rr_type::OPIN:
829829
draw_rr_pin(inode, color, g);
830830
if (with_edges) draw_rr_edges(inode, g);
831831
break;

‎vpr/src/pack/sync_netlists_to_routing_flat.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ static void get_intra_cluster_connections(const RouteTree& tree, std::vector<std
100100
auto type = rr_graph.node_type(node.inode);
101101
auto parent_type = rr_graph.node_type(parent->inode);
102102

103-
if ((type == t_rr_type::IPIN || type == OPIN) && (parent_type == t_rr_type::IPIN || parent_type == OPIN)) {
103+
if ((type == t_rr_type::IPIN || type == t_rr_type::OPIN) && (parent_type == t_rr_type::IPIN || parent_type == t_rr_type::OPIN)) {
104104
auto clb = get_cluster_block_from_rr_node(node.inode);
105105
auto parent_clb = get_cluster_block_from_rr_node(parent->inode);
106106
if (clb == parent_clb)
@@ -336,7 +336,7 @@ static void sync_clustered_netlist_to_routing(void) {
336336
int clb_nets_so_far = 0;
337337
for (auto& rt_node : tree->all_nodes()) {
338338
auto node_type = rr_graph.node_type(rt_node.inode);
339-
if (node_type != t_rr_type::IPIN && node_type != OPIN)
339+
if (node_type != t_rr_type::IPIN && node_type != t_rr_type::OPIN)
340340
continue;
341341

342342
auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rt_node.inode),
@@ -353,7 +353,7 @@ static void sync_clustered_netlist_to_routing(void) {
353353
/* OPIN on the tile: create a new clb_net_id and add all ports & pins into here
354354
* Due to how the route tree is traversed, all nodes until the next OPIN on the tile will
355355
* be under this OPIN, so this is valid (we don't need to get the branch explicitly) */
356-
if (node_type == OPIN) {
356+
if (node_type == t_rr_type::OPIN) {
357357
std::string net_name;
358358
net_name = atom_ctx.netlist().net_name(parent_net_id) + "_" + std::to_string(clb_nets_so_far);
359359
clb_net_id = clb_netlist.create_net(net_name);
@@ -376,7 +376,7 @@ static void sync_clustered_netlist_to_routing(void) {
376376
VTR_ASSERT_MSG(false, "Unsupported port type");
377377
port_id = clb_netlist.create_port(clb, pb_graph_pin->port->name, pb_graph_pin->port->num_pins, port_type);
378378
}
379-
PinType pin_type = node_type == OPIN ? PinType::DRIVER : PinType::SINK;
379+
PinType pin_type = node_type == t_rr_type::OPIN ? PinType::DRIVER : PinType::SINK;
380380

381381
ClusterPinId new_pin = clb_netlist.create_pin(port_id, pb_graph_pin->pin_number, clb_net_id, pin_type, pb_graph_pin->pin_count_in_cluster);
382382
clb_netlist.set_pin_net(new_pin, pin_type, clb_net_id);

‎vpr/src/route/check_route.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -332,7 +332,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) {
332332
VTR_ASSERT(abs(from_layer - to_layer) <= 1);
333333
switch (from_type) {
334334
case t_rr_type::SOURCE:
335-
VTR_ASSERT(to_type == OPIN);
335+
VTR_ASSERT(to_type == t_rr_type::OPIN);
336336

337337
//The OPIN should be contained within the bounding box of it's connected source
338338
if (from_xlow <= to_xlow
@@ -353,12 +353,12 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) {
353353
/* SINKS are adjacent to not connected */
354354
break;
355355

356-
case OPIN:
356+
case t_rr_type::OPIN:
357357
from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer});
358358
if (to_type == CHANX || to_type == CHANY) {
359359
num_adj += 1; //adjacent
360360
} else if (is_flat) {
361-
VTR_ASSERT(to_type == OPIN || to_type == t_rr_type::IPIN); // If pin is located inside a cluster
361+
VTR_ASSERT(to_type == t_rr_type::OPIN || to_type == t_rr_type::IPIN); // If pin is located inside a cluster
362362
return true;
363363
} else {
364364
VTR_ASSERT(to_type == t_rr_type::IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */
@@ -370,7 +370,7 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) {
370370
case t_rr_type::IPIN:
371371
from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer});
372372
if (is_flat) {
373-
VTR_ASSERT(to_type == OPIN || to_type == t_rr_type::IPIN || to_type == SINK);
373+
VTR_ASSERT(to_type == t_rr_type::OPIN || to_type == t_rr_type::IPIN || to_type == SINK);
374374
} else {
375375
VTR_ASSERT(to_type == SINK);
376376
}

‎vpr/src/route/router_lookahead_compressed_map.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -410,7 +410,7 @@ float CompressedMapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId
410410
float delay_cost = 0.;
411411
float cong_cost = 0.;
412412

413-
if (from_rr_type == CHANX || from_rr_type == CHANY || from_rr_type == t_rr_type::SOURCE || from_rr_type == OPIN) {
413+
if (from_rr_type == CHANX || from_rr_type == CHANY || from_rr_type == t_rr_type::SOURCE || from_rr_type == t_rr_type::OPIN) {
414414
// Get the total cost using the combined delay and congestion costs
415415
std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream);
416416
return delay_cost + cong_cost;
@@ -438,7 +438,7 @@ std::pair<float, float> CompressedMapLookahead::get_expected_delay_and_cong(RRNo
438438
float expected_cong_cost = std::numeric_limits<float>::infinity();
439439

440440
e_rr_type from_type = rr_graph.node_type(from_node);
441-
if (from_type == t_rr_type::SOURCE || from_type == OPIN) {
441+
if (from_type == t_rr_type::SOURCE || from_type == t_rr_type::OPIN) {
442442
//When estimating costs from a SOURCE/OPIN we look-up to find which wire types (and the
443443
//cost to reach them) in src_opin_delays. Once we know what wire types are
444444
//reachable, we query the f_wire_cost_map (i.e. the wire lookahead) to get the final

‎vpr/src/route/rr_graph.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2496,7 +2496,7 @@ static void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder,
24962496
int x_offset = x_offset_vec[pin_coord];
24972497
int y_offset = y_offset_vec[pin_coord];
24982498
e_side pin_side = pin_sides_vec[pin_coord];
2499-
auto node_type = (pin_type == DRIVER) ? OPIN : IPIN;
2499+
auto node_type = (pin_type == DRIVER) ? t_rr_type::OPIN : IPIN;
25002500
RRNodeId node_id = node_lookup.find_node(layer,
25012501
i + x_offset,
25022502
j + y_offset,
@@ -2717,7 +2717,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder,
27172717
total_pin_Fc += Fc[pin_index][iseg];
27182718
}
27192719

2720-
RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, OPIN, pin_index, side);
2720+
RRNodeId node_index = rr_graph_builder.node_lookup().find_node(layer, i, j, t_rr_type::OPIN, pin_index, side);
27212721
VTR_ASSERT(node_index);
27222722

27232723
for (auto connected_layer : get_layers_pin_is_connected_to(type, layer, pin_index)) {

‎vpr/src/route/rr_graph_timing_params.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -148,7 +148,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
148148

149149
}
150150
/* End node is CHANX or CHANY */
151-
else if (from_rr_type == OPIN) {
151+
else if (from_rr_type == t_rr_type::OPIN) {
152152
for (t_edge_size iedge = 0; iedge < rr_graph.num_edges(rr_id); iedge++) {
153153
switch_index = rr_graph.edge_switch(rr_id, iedge);
154154
to_node = size_t(rr_graph.edge_sink_node(rr_id, iedge));

‎vpr/src/timing/VprTimingGraphResolver.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -342,7 +342,7 @@ void VprTimingGraphResolver::get_detailed_interconnect_components_helper(std::ve
342342
// Process the current interconnect component if it is of type OPIN, CHANX, CHANY, IPIN
343343
// Only process SOURCE, SINK in debug report mode
344344
auto rr_type = rr_graph.node_type(RRNodeId(current_node->inode));
345-
if (rr_type == OPIN
345+
if (rr_type == t_rr_type::OPIN
346346
|| rr_type == t_rr_type::IPIN
347347
|| rr_type == CHANX
348348
|| rr_type == CHANY

0 commit comments

Comments
 (0)