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soheilshahrouzsoheilshahrouz
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IPIN ---> t_rr_type::IPIN
1 parent e1386a2 commit 5a118c0

11 files changed

+37
-37
lines changed

‎libs/librrgraph/src/base/check_rr_graph.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -155,11 +155,11 @@ void check_rr_graph(const RRGraphView& rr_graph,
155155
* - OPIN -> CHAN connections (unique rr_node for OPIN nodes on multiple sides)
156156
*/
157157
bool is_chan_to_chan = (rr_type == CHANX || rr_type == CHANY) && (to_rr_type == CHANY || to_rr_type == CHANX);
158-
bool is_chan_to_ipin = (rr_type == CHANX || rr_type == CHANY) && to_rr_type == IPIN;
158+
bool is_chan_to_ipin = (rr_type == CHANX || rr_type == CHANY) && to_rr_type == t_rr_type::IPIN;
159159
bool is_opin_to_chan = rr_type == OPIN && (to_rr_type == CHANX || to_rr_type == CHANY);
160160
bool is_internal_edge = false;
161161
if (is_flat) {
162-
is_internal_edge = (rr_type == IPIN && to_rr_type == IPIN) || (rr_type == OPIN && to_rr_type == OPIN);
162+
is_internal_edge = (rr_type == t_rr_type::IPIN && to_rr_type == t_rr_type::IPIN) || (rr_type == OPIN && to_rr_type == OPIN);
163163
}
164164
if (!(is_chan_to_chan || is_chan_to_ipin || is_opin_to_chan || is_internal_edge)) {
165165
VPR_ERROR(VPR_ERROR_ROUTE,
@@ -168,7 +168,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
168168
}
169169

170170
//Between two wire segments
171-
VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == IPIN, "Expect channel type or input pin type");
171+
VTR_ASSERT_MSG(to_rr_type == CHANX || to_rr_type == CHANY || to_rr_type == t_rr_type::IPIN, "Expect channel type or input pin type");
172172
VTR_ASSERT_MSG(rr_type == CHANX || rr_type == CHANY || rr_type == OPIN, "Expect channel type or output pin type");
173173

174174
//While multiple connections between the same wires can be electrically legal,
@@ -240,7 +240,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
240240

241241
t_physical_tile_type_ptr type = grid.get_physical_type({xlow, ylow, layer_num});
242242

243-
if (rr_type == IPIN || rr_type == OPIN) {
243+
if (rr_type == t_rr_type::IPIN || rr_type == OPIN) {
244244
// #TODO: No edges are added for internal pins. However, they need to be checked somehow!
245245
if (ptc_num >= type->num_pins) {
246246
VTR_LOG_ERROR("in check_rr_graph: node %d (%s) type: %s is internal node.\n",
@@ -255,7 +255,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
255255
* For simplicity, carry-chain input pin are entirely ignored in this test
256256
*/
257257
bool is_chain = false;
258-
if (rr_type == IPIN) {
258+
if (rr_type == t_rr_type::IPIN) {
259259
for (const t_fc_specification& fc_spec : types[type->index].fc_specs) {
260260
if (fc_spec.fc_value == 0 && fc_spec.seg_index == 0) {
261261
is_chain = true;
@@ -273,7 +273,7 @@ void check_rr_graph(const RRGraphView& rr_graph,
273273
|| rr_graph.node_type(rr_node) == CHANY);
274274

275275
if (!is_chain && !is_fringe && !is_wire) {
276-
if (rr_graph.node_type(rr_node) == IPIN || rr_graph.node_type(rr_node) == OPIN) {
276+
if (rr_graph.node_type(rr_node) == t_rr_type::IPIN || rr_graph.node_type(rr_node) == OPIN) {
277277
if (has_adjacent_channel(rr_graph, grid, node)) {
278278
auto block_type = grid.get_physical_type({rr_graph.node_xlow(rr_node),
279279
rr_graph.node_ylow(rr_node),
@@ -320,7 +320,7 @@ static bool rr_node_is_global_clb_ipin(const RRGraphView& rr_graph, const Device
320320
rr_graph.node_ylow(inode),
321321
rr_graph.node_layer(inode)});
322322

323-
if (rr_graph.node_type(inode) != IPIN)
323+
if (rr_graph.node_type(inode) != t_rr_type::IPIN)
324324
return (false);
325325

326326
ipin = rr_graph.node_pin_num(inode);
@@ -413,7 +413,7 @@ void check_rr_node(const RRGraphView& rr_graph,
413413
}
414414
break;
415415
}
416-
case IPIN:
416+
case t_rr_type::IPIN:
417417
case OPIN:
418418
if (type == nullptr) {
419419
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
@@ -475,7 +475,7 @@ void check_rr_node(const RRGraphView& rr_graph,
475475
break;
476476

477477
case OPIN:
478-
case IPIN:
478+
case t_rr_type::IPIN:
479479
class_type = get_pin_type_from_pin_physical_num(type, ptc_num);
480480
if (ptc_num >= pin_max_ptc
481481
|| class_type != ((rr_type == OPIN) ? DRIVER : RECEIVER)) {
@@ -592,7 +592,7 @@ static bool has_adjacent_channel(const RRGraphView& rr_graph, const DeviceGrid&
592592
/* TODO: this function should be reworked later to adapt RRGraphView interface
593593
* once xlow(), ylow(), side() APIs are implemented
594594
*/
595-
VTR_ASSERT(rr_graph.node_type(node.id()) == IPIN || rr_graph.node_type(node.id()) == OPIN);
595+
VTR_ASSERT(rr_graph.node_type(node.id()) == t_rr_type::IPIN || rr_graph.node_type(node.id()) == OPIN);
596596

597597
if ((rr_graph.node_xlow(node.id()) == 0 && !rr_graph.is_node_on_specific_side(node.id(), RIGHT)) //left device edge connects only along block's right side
598598
|| (rr_graph.node_ylow(node.id()) == int(grid.height() - 1) && !rr_graph.is_node_on_specific_side(node.id(), BOTTOM)) //top device edge connects only along block's bottom side

‎libs/librrgraph/src/base/rr_graph_builder.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) {
4949
node_lookup_.add_node(node, node_layer, iy, ix, node_type, node_ptc_num, TOTAL_2D_SIDES[0]);
5050
break;
5151
case OPIN:
52-
case IPIN:
52+
case t_rr_type::IPIN:
5353
for (const e_side& side : TOTAL_2D_SIDES) {
5454
if (node_storage_.is_node_on_specific_side(node, side)) {
5555
node_lookup_.add_node(node,node_layer, ix, iy, node_type, node_ptc_num, side);

‎vpr/src/base/vpr_types.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1361,7 +1361,7 @@ struct t_det_routing_arch {
13611361
std::string read_rr_edge_override_filename;
13621362
};
13631363

1364-
constexpr bool is_pin(e_rr_type type) { return (type == IPIN || type == OPIN); }
1364+
constexpr bool is_pin(e_rr_type type) { return (type == t_rr_type::IPIN || type == OPIN); }
13651365
constexpr bool is_chan(e_rr_type type) { return (type == CHANX || type == CHANY); }
13661366
constexpr bool is_src_sink(e_rr_type type) { return (type == t_rr_type::SOURCE || type == t_rr_type::SINK); }
13671367

‎vpr/src/draw/draw_basic.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -356,7 +356,7 @@ void draw_congestion(ezgl::renderer* g) {
356356
draw_rr_chan(inode, color, g);
357357
break;
358358

359-
case IPIN: //fallthrough
359+
case t_rr_type::IPIN: //fallthrough
360360
case OPIN:
361361
draw_rr_pin(inode, color, g);
362362
break;
@@ -655,7 +655,7 @@ void draw_partial_route(const std::vector<RRNodeId>& rr_nodes_to_draw, ezgl::ren
655655
draw_rr_pin(inode, color, g);
656656
break;
657657
}
658-
case IPIN: {
658+
case t_rr_type::IPIN: {
659659
draw_rr_pin(inode, color, g);
660660
if (edge_visibility.visible) {
661661
g->set_color(color, edge_visibility.alpha);

‎vpr/src/draw/draw_rr.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -69,7 +69,7 @@ void draw_rr(ezgl::renderer* g) {
6969
case OPIN:
7070
draw_state->draw_rr_node[inode].color = ezgl::PINK;
7171
break;
72-
case IPIN:
72+
case t_rr_type::IPIN:
7373
draw_state->draw_rr_node[inode].color = blk_LIGHTSKYBLUE;
7474
break;
7575
case t_rr_type::SOURCE:
@@ -108,7 +108,7 @@ void draw_rr(ezgl::renderer* g) {
108108
draw_rr_edges(inode, g);
109109
break;
110110

111-
case IPIN:
111+
case t_rr_type::IPIN:
112112
draw_rr_pin(inode, draw_state->draw_rr_node[inode].color, g);
113113
draw_rr_edges(inode, g);
114114
break;
@@ -287,8 +287,8 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
287287
from_type = rr_graph.node_type(rr_node);
288288

289289
if ((draw_state->draw_rr_toggle == DRAW_NODES_RR)
290-
|| (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == OPIN || from_type == t_rr_type::SOURCE || from_type == IPIN))
291-
|| (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == t_rr_type::SOURCE || from_type == IPIN))) {
290+
|| (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR && (from_type == OPIN || from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN))
291+
|| (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_CBOX_RR && (from_type == t_rr_type::SOURCE || from_type == t_rr_type::IPIN))) {
292292
return; /* Nothing to draw. */
293293
}
294294

@@ -318,7 +318,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
318318
}
319319
draw_pin_to_chan_edge(inode, to_node, g);
320320
break;
321-
case IPIN:
321+
case t_rr_type::IPIN:
322322
if (rgb_is_same(draw_state->draw_rr_node[inode].color, ezgl::MAGENTA)) {
323323
ezgl::color color = draw_state->draw_rr_node[to_node].color;
324324
g->set_color(color, transparency_factor);
@@ -340,7 +340,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
340340

341341
case CHANX: /* from_type */
342342
switch (to_type) {
343-
case IPIN:
343+
case t_rr_type::IPIN:
344344
if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) {
345345
break;
346346
}
@@ -410,7 +410,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
410410

411411
case CHANY: /* from_type */
412412
switch (to_type) {
413-
case IPIN:
413+
case t_rr_type::IPIN:
414414
if (draw_state->draw_rr_toggle == DRAW_NODES_SBOX_RR) {
415415
break;
416416
}
@@ -478,7 +478,7 @@ void draw_rr_edges(RRNodeId inode, ezgl::renderer* g) {
478478
break;
479479
}
480480
break;
481-
case IPIN: // from_type
481+
case t_rr_type::IPIN: // from_type
482482
switch (to_type) {
483483
case t_rr_type::SINK:
484484
g->set_color(ezgl::DARK_SLATE_BLUE, transparency_factor);
@@ -686,7 +686,7 @@ RRNodeId draw_check_rr_node_hit(float click_x, float click_y) {
686686
continue; /* Don't check RR nodes on currently invisible layers*/
687687
}
688688
switch (rr_graph.node_type(inode)) {
689-
case IPIN:
689+
case t_rr_type::IPIN:
690690
case OPIN: {
691691
int i = rr_graph.node_xlow(inode);
692692
int j = rr_graph.node_ylow(inode);
@@ -821,7 +821,7 @@ void draw_rr_costs(ezgl::renderer* g, const vtr::vector<RRNodeId, float>& rr_cos
821821
if (with_edges) draw_rr_edges(inode, g);
822822
break;
823823

824-
case IPIN: //fallthrough
824+
case t_rr_type::IPIN: //fallthrough
825825
draw_rr_pin(inode, color, g);
826826
if (with_edges) draw_rr_edges(inode, g);
827827
break;

‎vpr/src/pack/sync_netlists_to_routing_flat.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ static void get_intra_cluster_connections(const RouteTree& tree, std::vector<std
100100
auto type = rr_graph.node_type(node.inode);
101101
auto parent_type = rr_graph.node_type(parent->inode);
102102

103-
if ((type == IPIN || type == OPIN) && (parent_type == IPIN || parent_type == OPIN)) {
103+
if ((type == t_rr_type::IPIN || type == OPIN) && (parent_type == t_rr_type::IPIN || parent_type == OPIN)) {
104104
auto clb = get_cluster_block_from_rr_node(node.inode);
105105
auto parent_clb = get_cluster_block_from_rr_node(parent->inode);
106106
if (clb == parent_clb)
@@ -336,7 +336,7 @@ static void sync_clustered_netlist_to_routing(void) {
336336
int clb_nets_so_far = 0;
337337
for (auto& rt_node : tree->all_nodes()) {
338338
auto node_type = rr_graph.node_type(rt_node.inode);
339-
if (node_type != IPIN && node_type != OPIN)
339+
if (node_type != t_rr_type::IPIN && node_type != OPIN)
340340
continue;
341341

342342
auto physical_tile = device_ctx.grid.get_physical_type({rr_graph.node_xlow(rt_node.inode),

‎vpr/src/route/check_route.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -358,19 +358,19 @@ static bool check_adjacent(RRNodeId from_node, RRNodeId to_node, bool is_flat) {
358358
if (to_type == CHANX || to_type == CHANY) {
359359
num_adj += 1; //adjacent
360360
} else if (is_flat) {
361-
VTR_ASSERT(to_type == OPIN || to_type == IPIN); // If pin is located inside a cluster
361+
VTR_ASSERT(to_type == OPIN || to_type == t_rr_type::IPIN); // If pin is located inside a cluster
362362
return true;
363363
} else {
364-
VTR_ASSERT(to_type == IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */
364+
VTR_ASSERT(to_type == t_rr_type::IPIN); /* direct OPIN to IPIN connections not necessarily adjacent */
365365
return true; /* Special case, direct OPIN to IPIN connections need not be adjacent */
366366
}
367367

368368
break;
369369

370-
case IPIN:
370+
case t_rr_type::IPIN:
371371
from_grid_type = device_ctx.grid.get_physical_type({from_xlow, from_ylow, from_layer});
372372
if (is_flat) {
373-
VTR_ASSERT(to_type == OPIN || to_type == IPIN || to_type == SINK);
373+
VTR_ASSERT(to_type == OPIN || to_type == t_rr_type::IPIN || to_type == SINK);
374374
} else {
375375
VTR_ASSERT(to_type == SINK);
376376
}

‎vpr/src/route/connection_router.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -477,7 +477,7 @@ void ConnectionRouter<Heap>::timing_driven_expand_neighbour(const RTExploredNode
477477
* Change this if you want to investigate route-throughs. */
478478
if (target_node != RRNodeId::INVALID()) {
479479
t_rr_type to_type = rr_graph_->node_type(to_node);
480-
if (to_type == IPIN) {
480+
if (to_type == t_rr_type::IPIN) {
481481
// Check if this IPIN leads to the target block
482482
// IPIN's of the target block should be contained within it's bounding box
483483
int to_xlow = rr_graph_->node_xlow(to_node);
@@ -758,7 +758,7 @@ void ConnectionRouter<Heap>::evaluate_timing_driven_node_costs(RTExploredNode* t
758758
//cost.
759759
cong_cost = 0.;
760760
}
761-
if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == IPIN) {
761+
if (conn_params_->router_opt_choke_points_ && is_flat_ && rr_graph_->node_type(to->index) == t_rr_type::IPIN) {
762762
auto find_res = conn_params_->connection_choking_spots_.find(to->index);
763763
if (find_res != conn_params_->connection_choking_spots_.end()) {
764764
cong_cost = cong_cost / pow(2, (float)find_res->second);
@@ -1047,7 +1047,7 @@ static inline bool relevant_node_to_target(const RRGraphView* rr_graph,
10471047
RRNodeId target_node) {
10481048
VTR_ASSERT_SAFE(rr_graph->node_type(target_node) == t_rr_type::SINK);
10491049
auto node_to_add_type = rr_graph->node_type(node_to_add);
1050-
return node_to_add_type != t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node);
1050+
return node_to_add_type != t_rr_type::t_rr_type::IPIN || node_in_same_physical_tile(node_to_add, target_node);
10511051
}
10521052

10531053
static inline void update_router_stats(RouterStats* router_stats,

‎vpr/src/route/router_lookahead_compressed_map.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -414,7 +414,7 @@ float CompressedMapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId
414414
// Get the total cost using the combined delay and congestion costs
415415
std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream);
416416
return delay_cost + cong_cost;
417-
} else if (from_rr_type == IPIN) { /* Change if you're allowing route-throughs */
417+
} else if (from_rr_type == t_rr_type::IPIN) { /* Change if you're allowing route-throughs */
418418
return (device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost);
419419
} else { /* Change this if you want to investigate route-throughs */
420420
return (0.);
@@ -502,7 +502,7 @@ std::pair<float, float> CompressedMapLookahead::get_expected_delay_and_cong(RRNo
502502
.c_str());
503503
expected_delay_cost = cost_entry.delay * params.criticality;
504504
expected_cong_cost = cost_entry.congestion * (1 - params.criticality);
505-
} else if (from_type == IPIN) { /* Change if you're allowing route-throughs */
505+
} else if (from_type == t_rr_type::IPIN) { /* Change if you're allowing route-throughs */
506506
return std::make_pair(0., device_ctx.rr_indexed_data[RRIndexedDataId(SINK_COST_INDEX)].base_cost);
507507
} else { /* Change this if you want to investigate route-throughs */
508508
return std::make_pair(0., 0.);

‎vpr/src/route/rr_graph_timing_params.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -99,7 +99,7 @@ void add_rr_graph_C_from_switches(float C_ipin_cblock) {
9999

100100
}
101101
/* End edge to CHANX or CHANY node. */
102-
else if (to_rr_type == IPIN) {
102+
else if (to_rr_type == t_rr_type::IPIN) {
103103
if (INCLUDE_TRACK_BUFFERS) {
104104
/* Implements sharing of the track to connection box buffer.
105105
* Such a buffer exists at every segment of the wire at which

‎vpr/src/timing/VprTimingGraphResolver.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -343,7 +343,7 @@ void VprTimingGraphResolver::get_detailed_interconnect_components_helper(std::ve
343343
// Only process SOURCE, SINK in debug report mode
344344
auto rr_type = rr_graph.node_type(RRNodeId(current_node->inode));
345345
if (rr_type == OPIN
346-
|| rr_type == IPIN
346+
|| rr_type == t_rr_type::IPIN
347347
|| rr_type == CHANX
348348
|| rr_type == CHANY
349349
|| ((rr_type == t_rr_type::SOURCE || rr_type == t_rr_type::SINK) && (detail_level() == e_timing_report_detail::DEBUG))) {

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