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Updated documentation to address the tiles tag addition
Signed-off-by: Alessandro Comodi <[email protected]>
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‎doc/src/arch/example_arch.xml

Lines changed: 84 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,12 @@
1-
<!-- VPR Architecture Specification File --><!-- Quick XML Primer:
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<!-- VPR Architecture Specification File -->
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<!-- Quick XML Primer:
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* Data is hierarchical and composed of tags (similar to HTML)
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* All tags must be of the form <foo>content</foo> OR <foo /> with the latter form indicating no content. Don't forget the slash at the end.
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* Inside a start tag you may specify attributes in the form key="value". Refer to manual for the valid attributes for each element.
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* Comments may be included anywhere in the document except inside a tag where it's attribute list is defined.
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* Comments may contain any characters except two dashes.
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--><!-- Architecture based off Stratix IV
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-->
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<!-- Architecture based off Stratix IV
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Use closest ifar architecture: K06 N10 45nm fc 0.15 area-delay optimized, scale to 40 nm using linear scaling
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n10k06l04.fc15.area1delay1.cmos45nm.bptm.cmos45nm.xml
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* because documentation sparser for soft logic (delays not in QUIP), harder to track down, not worth our time considering the level of accuracy is approximate
@@ -21,7 +23,8 @@
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created 4 18x18 mulitpliers, logiclocked them to a single DSP block, compile
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result - 2 18x18 multipliers got packed together, the other 2 got ejected out of the logiclock region without error
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conclusion - just take the 600 MHz as is, and Quartus II logiclock hasn't fixed the bug that I've seen it do to registers when I worked at Altera (ie. eject without warning)
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--><architecture>
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-->
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<architecture>
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<!-- ODIN II specific config -->
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<models>
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<model name="multiply">
@@ -74,23 +77,73 @@
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</output_ports>
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</model>
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</models>
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<tiles>
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<tile name="io" capacity="8">
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<equivalent_sites>
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<site pb_type="io"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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</tile>
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<tile name="clb">
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<equivalent_sites>
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<site pb_type="clb"/>
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</equivalent_sites>
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<input name="I" num_pins="33" equivalent="full"/>
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<output name="O" num_pins="10" equivalent="instance"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</tile>
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<tile name="mult_36" height="4">
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<equivalent_sites>
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<site pb_type="mult_36"/>
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</equivalent_sites>
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<input name="a" num_pins="36"/>
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<input name="b" num_pins="36"/>
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<output name="out" num_pins="72"/>
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<pinlocations pattern="spread"/>
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</tile>
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<tile name="memory" height="6">
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<equivalent_sites>
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<site pb_type="memory"/>
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</equivalent_sites>
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<input name="addr1" num_pins="17"/>
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<input name="addr2" num_pins="17"/>
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<input name="data" num_pins="72"/>
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<input name="we1" num_pins="1"/>
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<input name="we2" num_pins="1"/>
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<output name="out" num_pins="72"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin (area optimized for N8-K6-L4 -->
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<layout>
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<auto_layout aspect_ratio="1.0">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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<!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
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<col type="mult_36" startx="4" starty="1" repeatx="8" priority="20"/>
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<col type="EMPTY" startx="4" repeatx="8" starty="1" priority="19"/>
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<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
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<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
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<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
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</auto_layout>
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</layout>
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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<!--Column of 'mult_36' with 'EMPTY' blocks wherever a 'mult_36' does not fit. Vertical offset by 1 for perimeter.-->
140+
<col type="mult_36" startx="4" starty="1" repeatx="8" priority="20"/>
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<col type="EMPTY" startx="4" repeatx="8" starty="1" priority="19"/>
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<!--Column of 'memory' with 'EMPTY' blocks wherever a 'memory' does not fit. Vertical offset by 1 for perimeter.-->
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<col type="memory" startx="2" starty="1" repeatx="8" priority="20"/>
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<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
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</auto_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="6065.520020" R_minW_pmos="18138.500000"/>
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<area grid_logic_tile_area="14813.392"/>
@@ -100,13 +153,13 @@
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
156+
<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.837e-11" mux_trans_size="2.630740" buf_size="27.645901"/>
107-
<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
109-
</switchlist>
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<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
161+
<switch type="mux" name="ipin_cblock" R="1516.380005" Cout="0." Cin="0.000000e+00" Tdel="7.247000e-11" mux_trans_size="1.222260" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment freq="1.000000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
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<mux name="0"/>
@@ -116,7 +169,7 @@
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</segmentlist>
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<complexblocklist>
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<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
119-
<pb_type name="io" capacity="8">
172+
<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
@@ -141,22 +194,14 @@
141194
</direct>
142195
</interconnect>
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</mode>
144-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<!-- IOs go on the periphery of the FPGA, for consistency,
146198
make it physically equivalent on all sides so that only one definition of I/Os is needed.
147199
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
148200
-->
149-
<pinlocations pattern="custom">
150-
<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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</pb_type>
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</pb_type>
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<pb_type name="clb">
158-
<input name="I" num_pins="33" equivalent="full"/> <!-- NOTE: Logically Equivalent -->
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<output name="O" num_pins="10" equivalent="instance"/> <!-- NOTE: Logically Equivalent -->
203+
<input name="I" num_pins="33" equivalent="full"/><!-- NOTE: Logically Equivalent -->
204+
<output name="O" num_pins="10" equivalent="instance"/><!-- NOTE: Logically Equivalent -->
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<clock name="clk" num_pins="1"/>
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<!-- Describe basic logic element -->
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<pb_type name="ble" num_pb="10">
@@ -209,12 +254,9 @@
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<complete name="clks" input="clb.clk" output="ble[9:0].clk"/>
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<direct name="clbouts" input="ble[9:0].out" output="clb.O"/>
211256
</interconnect>
212-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</pb_type>
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</pb_type>
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<!-- This is the 36*36 uniform mult -->
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<pb_type name="mult_36" height="4">
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<pb_type name="mult_36">
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<input name="a" num_pins="36"/>
219261
<input name="b" num_pins="36"/>
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<output name="out" num_pins="72"/>
@@ -304,11 +346,9 @@
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</mode>
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<fc_in type="frac">0.15</fc_in>
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<fc_out type="frac">0.10</fc_out>
307-
<pinlocations pattern="spread"/>
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</pb_type>
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</pb_type>
310350
<!-- Memory based off Stratix IV 144K memory. Setup time set to match flip-flop setup time at 45 nm. Clock to q based off 144K max MHz -->
311-
<pb_type name="memory" height="6">
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<pb_type name="memory">
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<input name="addr1" num_pins="17"/>
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<input name="addr2" num_pins="17"/>
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<input name="data" num_pins="72"/>
@@ -492,8 +532,6 @@
492532
<direct name="clk" input="memory.clk" output="mem_18194x9_sp.clk"/>
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</interconnect>
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</mode>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
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<pinlocations pattern="spread"/>
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</pb_type>
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</pb_type>
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</complexblocklist>
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</architecture>
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</architecture>

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