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acomodiacomodi
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updated all test architecture files with pretty-print and tile tags
Signed-off-by: Alessandro Comodi <[email protected]>
1 parent fab3eb6 commit c112067

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202 files changed

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‎libs/libarchfpga/arch/mult_luts_arch.xml

Lines changed: 620 additions & 605 deletions
Large diffs are not rendered by default.

‎libs/libarchfpga/arch/sample_arch.xml

Lines changed: 129 additions & 137 deletions
Large diffs are not rendered by default.

‎utils/fasm/test/test_fasm_arch.xml

Lines changed: 29 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,34 @@
11
<architecture>
22
<models/>
3-
3+
<tiles>
4+
<tile name="io" capacity="8">
5+
<equivalent_sites>
6+
<site pb_type="io"/>
7+
</equivalent_sites>
8+
<input name="outpad" num_pins="1"/>
9+
<output name="inpad" num_pins="1"/>
10+
<clock name="clock" num_pins="1"/>
11+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
12+
<pinlocations pattern="custom">
13+
<loc side="left">io.outpad io.inpad io.clock</loc>
14+
<loc side="top">io.outpad io.inpad io.clock</loc>
15+
<loc side="right">io.outpad io.inpad io.clock</loc>
16+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
17+
</pinlocations>
18+
</tile>
19+
<tile name="clb">
20+
<equivalent_sites>
21+
<site pb_type="clb"/>
22+
</equivalent_sites>
23+
<input name="I" num_pins="33" equivalent="full"/>
24+
<output name="O" num_pins="20" equivalent="none"/>
25+
<clock name="clk" num_pins="1"/>
26+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
27+
<pinlocations pattern="spread"/>
28+
</tile>
29+
</tiles>
430
<layout>
5-
<fixed_layout height="10" width="10" name="test" >
31+
<fixed_layout height="10" width="10" name="test">
632
<perimeter type="io" priority="100">
733
<metadata>
834
<meta name="type">io</meta>
@@ -18,7 +44,6 @@
1844
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
1945
</fixed_layout>
2046
</layout>
21-
2247
<device>
2348
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
2449
<area grid_logic_tile_area="53894"/>
@@ -40,13 +65,11 @@
4065
<cb type="pattern">1 1 1 1</cb>
4166
</segment>
4267
</segmentlist>
43-
4468
<complexblocklist>
45-
<pb_type name="io" capacity="8">
69+
<pb_type name="io">
4670
<input name="outpad" num_pins="1"/>
4771
<output name="inpad" num_pins="1"/>
4872
<clock name="clock" num_pins="1"/>
49-
5073
<mode name="inpad">
5174
<metadata>
5275
<meta name="mode">inpad</meta>
@@ -62,7 +85,6 @@
6285
</metadata>
6386
</direct>
6487
</interconnect>
65-
6688
</mode>
6789
<mode name="outpad">
6890
<pb_type name="outpad" blif_model=".output" num_pb="1">
@@ -74,25 +96,14 @@
7496
</direct>
7597
</interconnect>
7698
</mode>
77-
7899
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
79-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
80-
81100
<!-- IOs go on the periphery of the FPGA, for consistency,
82101
make it physically equivalent on all sides so that only one definition of I/Os is needed.
83102
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
84103
-->
85-
<pinlocations pattern="custom">
86-
<loc side="left">io.outpad io.inpad io.clock</loc>
87-
<loc side="top">io.outpad io.inpad io.clock</loc>
88-
<loc side="right">io.outpad io.inpad io.clock</loc>
89-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
90-
</pinlocations>
91-
92104
<!-- Place I/Os on the sides of the FPGA -->
93105
<power method="ignore"/>
94106
</pb_type>
95-
96107
<pb_type name="clb">
97108
<input name="I" num_pins="33" equivalent="full"/>
98109
<output name="O" num_pins="20" equivalent="none"/>
@@ -101,7 +112,6 @@
101112
<input name="in" num_pins="6"/>
102113
<output name="out" num_pins="2"/>
103114
<clock name="clk" num_pins="1"/>
104-
105115
<mode name="n2_lut5">
106116
<pb_type name="lut5inter" num_pb="1">
107117
<input name="in" num_pins="5"/>
@@ -111,7 +121,6 @@
111121
<input name="in" num_pins="5"/>
112122
<output name="out" num_pins="1"/>
113123
<clock name="clk" num_pins="1"/>
114-
115124
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
116125
<input name="in" num_pins="5" port_class="lut_in"/>
117126
<output name="out" num_pins="1" port_class="lut_out"/>
@@ -123,15 +132,13 @@
123132
235e-12
124133
</delay_matrix>
125134
</pb_type>
126-
127135
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
128136
<input name="D" num_pins="1" port_class="D"/>
129137
<output name="Q" num_pins="1" port_class="Q"/>
130138
<clock name="clk" num_pins="1" port_class="clock"/>
131139
<T_setup value="66e-12" port="ff.D" clock="clk"/>
132140
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
133141
</pb_type>
134-
135142
<interconnect>
136143
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
137144
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
@@ -182,7 +189,6 @@
182189
<input name="in" num_pins="6"/>
183190
<output name="out" num_pins="1"/>
184191
<clock name="clk" num_pins="1"/>
185-
186192
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
187193
<input name="in" num_pins="6" port_class="lut_in"/>
188194
<output name="out" num_pins="1" port_class="lut_out"/>
@@ -201,7 +207,6 @@
201207
</meta>
202208
</metadata>
203209
</pb_type>
204-
205210
<!-- Define flip-flop -->
206211
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
207212
<input name="D" num_pins="1" port_class="D"/>
@@ -210,7 +215,6 @@
210215
<T_setup value="66e-12" port="ff.D" clock="clk"/>
211216
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
212217
</pb_type>
213-
214218
<interconnect>
215219
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
216220
<direct name="direct2" input="lut6.out" output="ff.D">
@@ -253,14 +257,9 @@
253257
</complete>
254258
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
255259
</complete>
256-
257260
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
258261
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
259262
</interconnect>
260-
261-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
262-
263-
<pinlocations pattern="spread"/>
264263
</pb_type>
265264
</complexblocklist>
266265
<power>

‎vpr/test/test_read_arch_metadata.xml

Lines changed: 28 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,32 @@
11
<architecture>
22
<models/>
3-
3+
<tiles>
4+
<tile name="io" capacity="8">
5+
<equivalent_sites>
6+
<site pb_type="io"/>
7+
</equivalent_sites>
8+
<input name="outpad" num_pins="1"/>
9+
<output name="inpad" num_pins="1"/>
10+
<clock name="clock" num_pins="1"/>
11+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
12+
<pinlocations pattern="custom">
13+
<loc side="left">io.outpad io.inpad io.clock</loc>
14+
<loc side="top">io.outpad io.inpad io.clock</loc>
15+
<loc side="right">io.outpad io.inpad io.clock</loc>
16+
<loc side="bottom">io.outpad io.inpad io.clock</loc>
17+
</pinlocations>
18+
</tile>
19+
<tile name="clb">
20+
<equivalent_sites>
21+
<site pb_type="clb"/>
22+
</equivalent_sites>
23+
<input name="I" num_pins="33" equivalent="full"/>
24+
<output name="O" num_pins="20" equivalent="none"/>
25+
<clock name="clk" num_pins="1"/>
26+
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
27+
<pinlocations pattern="spread"/>
28+
</tile>
29+
</tiles>
430
<layout>
531
<auto_layout aspect_ratio="1.0">
632
<perimeter type="io" priority="100">
@@ -19,7 +45,6 @@
1945
<col type="EMPTY" startx="2" repeatx="8" starty="1" priority="19"/>
2046
</auto_layout>
2147
</layout>
22-
2348
<device>
2449
<sizing R_minW_nmos="8926" R_minW_pmos="16067"/>
2550
<area grid_logic_tile_area="53894"/>
@@ -41,16 +66,14 @@
4166
<cb type="pattern">1 1 1 1</cb>
4267
</segment>
4368
</segmentlist>
44-
4569
<complexblocklist>
46-
<pb_type name="io" capacity="8">
70+
<pb_type name="io">
4771
<metadata>
4872
<meta name="pb_type_type">pb_type = io</meta>
4973
</metadata>
5074
<input name="outpad" num_pins="1"/>
5175
<output name="inpad" num_pins="1"/>
5276
<clock name="clock" num_pins="1"/>
53-
5477
<mode name="inpad">
5578
<metadata>
5679
<meta name="mode">inpad</meta>
@@ -66,7 +89,6 @@
6689
</metadata>
6790
</direct>
6891
</interconnect>
69-
7092
</mode>
7193
<mode name="outpad">
7294
<pb_type name="outpad" blif_model=".output" num_pb="1">
@@ -78,25 +100,14 @@
78100
</direct>
79101
</interconnect>
80102
</mode>
81-
82103
<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
83-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
84-
85104
<!-- IOs go on the periphery of the FPGA, for consistency,
86105
make it physically equivalent on all sides so that only one definition of I/Os is needed.
87106
If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
88107
-->
89-
<pinlocations pattern="custom">
90-
<loc side="left">io.outpad io.inpad io.clock</loc>
91-
<loc side="top">io.outpad io.inpad io.clock</loc>
92-
<loc side="right">io.outpad io.inpad io.clock</loc>
93-
<loc side="bottom">io.outpad io.inpad io.clock</loc>
94-
</pinlocations>
95-
96108
<!-- Place I/Os on the sides of the FPGA -->
97109
<power method="ignore"/>
98110
</pb_type>
99-
100111
<pb_type name="clb">
101112
<input name="I" num_pins="33" equivalent="full"/>
102113
<output name="O" num_pins="20" equivalent="none"/>
@@ -105,7 +116,6 @@
105116
<input name="in" num_pins="6"/>
106117
<output name="out" num_pins="2"/>
107118
<clock name="clk" num_pins="1"/>
108-
109119
<mode name="n2_lut5">
110120
<pb_type name="lut5inter" num_pb="1">
111121
<input name="in" num_pins="5"/>
@@ -115,7 +125,6 @@
115125
<input name="in" num_pins="5"/>
116126
<output name="out" num_pins="1"/>
117127
<clock name="clk" num_pins="1"/>
118-
119128
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut">
120129
<input name="in" num_pins="5" port_class="lut_in"/>
121130
<output name="out" num_pins="1" port_class="lut_out"/>
@@ -127,15 +136,13 @@
127136
235e-12
128137
</delay_matrix>
129138
</pb_type>
130-
131139
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
132140
<input name="D" num_pins="1" port_class="D"/>
133141
<output name="Q" num_pins="1" port_class="Q"/>
134142
<clock name="clk" num_pins="1" port_class="clock"/>
135143
<T_setup value="66e-12" port="ff.D" clock="clk"/>
136144
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
137145
</pb_type>
138-
139146
<interconnect>
140147
<direct name="direct1" input="ble5.in[4:0]" output="lut5[0:0].in[4:0]"/>
141148
<direct name="direct2" input="lut5[0:0].out" output="ff[0:0].D">
@@ -168,7 +175,6 @@
168175
<input name="in" num_pins="6"/>
169176
<output name="out" num_pins="1"/>
170177
<clock name="clk" num_pins="1"/>
171-
172178
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut">
173179
<input name="in" num_pins="6" port_class="lut_in"/>
174180
<output name="out" num_pins="1" port_class="lut_out"/>
@@ -181,7 +187,6 @@
181187
261e-12
182188
</delay_matrix>
183189
</pb_type>
184-
185190
<!-- Define flip-flop -->
186191
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
187192
<input name="D" num_pins="1" port_class="D"/>
@@ -190,7 +195,6 @@
190195
<T_setup value="66e-12" port="ff.D" clock="clk"/>
191196
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
192197
</pb_type>
193-
194198
<interconnect>
195199
<direct name="direct1" input="ble6.in" output="lut6[0:0].in"/>
196200
<direct name="direct2" input="lut6.out" output="ff.D">
@@ -217,14 +221,9 @@
217221
</complete>
218222
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
219223
</complete>
220-
221224
<direct name="clbouts1" input="fle[9:0].out[0:0]" output="clb.O[9:0]"/>
222225
<direct name="clbouts2" input="fle[9:0].out[1:1]" output="clb.O[19:10]"/>
223226
</interconnect>
224-
225-
<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.10"/>
226-
227-
<pinlocations pattern="spread"/>
228227
</pb_type>
229228
</complexblocklist>
230229
<power>

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