vpr: remove equivalent sites from the physical tile type

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/arch_util.cpp

@@ -536,6 +536,18 @@ t_logical_block_type SetupEmptyLogicalType() {
     return type;
 }
 
+std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type) {
+    std::unordered_set<t_logical_block_type_ptr> equivalent_sites;
+
+    for (auto& sub_tile : type->sub_tiles) {
+        for (auto& logical_block : sub_tile.equivalent_sites) {
+            equivalent_sites.insert(logical_block);
+        }
+    }
+
+    return equivalent_sites;
+}
+
 void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
                                               char* new_name,
                                               t_pb_type* copy) {

libs/libarchfpga/src/arch_util.h

@@ -2,6 +2,7 @@
 #define ARCH_UTIL_H
 
 #include <regex>
+#include <unordered_set>
 #include "physical_types.h"
 
 class InstPort {
@@ -48,6 +49,8 @@ t_port* findPortByName(const char* name, t_pb_type* pb_type, int* high_index, in
 t_physical_tile_type SetupEmptyPhysicalType();
 t_logical_block_type SetupEmptyLogicalType();
 
+std::unordered_set<t_logical_block_type_ptr> get_equivalent_sites_set(t_physical_tile_type_ptr type);
+
 void alloc_and_load_default_child_for_pb_type(t_pb_type* pb_type,
                                               char* new_name,
                                               t_pb_type* copy);

libs/libarchfpga/src/echo_arch.cpp

@@ -1,9 +1,11 @@
 #include <cstring>
 #include <cstdlib>
 #include <vector>
+#include <unordered_set>
 
 #include "echo_arch.h"
 #include "arch_types.h"
+#include "arch_util.h"
 #include "vtr_list.h"
 #include "vtr_util.h"
 #include "vtr_memory.h"
@@ -103,7 +105,9 @@ void EchoArch(const char* EchoFile,
         int index = Type.index;
         fprintf(Echo, "\tindex: %d\n", index);
 
-        for (auto LogicalBlock : Type.equivalent_sites) {
+        auto equivalent_sites = get_equivalent_sites_set(&Type);
+
+        for (auto LogicalBlock : equivalent_sites) {
             fprintf(Echo, "\nEquivalent Site: %s\n", LogicalBlock->name);
         }
         fprintf(Echo, "\n");

libs/libarchfpga/src/physical_types.h

@@ -575,6 +575,7 @@ constexpr int DEFAULT_SWITCH = -2;
 struct t_physical_tile_type {
     char* name = nullptr;
     int num_pins = 0;
+    int num_inst_pins = 0;
     int num_input_pins = 0;
     int num_output_pins = 0;
     int num_clock_pins = 0;
@@ -609,8 +610,6 @@ struct t_physical_tile_type {
 
     std::vector<t_sub_tile> sub_tiles;
 
-    std::vector<t_logical_block_type_ptr> equivalent_sites;
-
     /* Unordered map indexed by the logical block index.
      * tile_block_pin_directs_map[logical block index][logical block pin] -> physical tile pin */
     std::unordered_map<int, vtr::bimap<t_logical_pin, t_physical_pin>> tile_block_pin_directs_map;

libs/libarchfpga/src/read_xml_arch_file.cpp

@@ -2903,14 +2903,16 @@ static void MarkIoTypes(std::vector<t_physical_tile_type>& PhysicalTileTypes) {
         type.is_input_type = false;
         type.is_output_type = false;
 
-        for (const auto& equivalent_site : type.equivalent_sites) {
+        auto equivalent_sites = get_equivalent_sites_set(&type);
+
+        for (const auto& equivalent_site : equivalent_sites) {
             if (block_type_contains_blif_model(equivalent_site, MODEL_INPUT)) {
                 type.is_input_type = true;
                 break;
             }
         }
 
-        for (const auto& equivalent_site : type.equivalent_sites) {
+        for (const auto& equivalent_site : equivalent_sites) {
             if (block_type_contains_blif_model(equivalent_site, MODEL_OUTPUT)) {
                 type.is_output_type = true;
                 break;
@@ -3110,7 +3112,6 @@ static void ProcessTileEquivalentSites(pugi::xml_node Parent,
         }
 
         if (0 == strcmp(LogicalBlockType->pb_type->name, Prop.c_str())) {
-            PhysicalTileType->equivalent_sites.push_back(LogicalBlockType);
             SubTile->equivalent_sites.push_back(LogicalBlockType);
 
             check_port_direct_mappings(PhysicalTileType, LogicalBlockType);
@@ -3460,6 +3461,7 @@ static void ProcessSubTiles(pugi::xml_node Node,
         PhysicalTileType->num_output_pins += capacity * pin_counts.output;
         PhysicalTileType->num_clock_pins += capacity * pin_counts.clock;
         PhysicalTileType->num_pins += capacity * pin_counts.total();
+        PhysicalTileType->num_inst_pins += pin_counts.total();
 
         /* Assign drivers and receivers count to Physical Tile Type */
         PhysicalTileType->num_receivers += capacity * pin_counts.input;
@@ -4960,16 +4962,17 @@ static void link_physical_logical_types(std::vector<t_physical_tile_type>& Physi
     for (auto& physical_tile : PhysicalTileTypes) {
         if (physical_tile.index == EMPTY_TYPE_INDEX) continue;
 
-        auto& equivalent_sites = physical_tile.equivalent_sites;
+        auto eq_sites_set = get_equivalent_sites_set(&physical_tile);
+        auto equivalent_sites = std::vector<t_logical_block_type_ptr>(eq_sites_set.begin(), eq_sites_set.end());
 
         auto criteria = [&physical_tile](const t_logical_block_type* lhs, const t_logical_block_type* rhs) {
-            int num_physical_pins = physical_tile.num_pins / physical_tile.capacity;
+            int num_pins = physical_tile.num_inst_pins;
 
             int lhs_num_logical_pins = lhs->pb_type->num_pins;
             int rhs_num_logical_pins = rhs->pb_type->num_pins;
 
-            int lhs_diff_num_pins = num_physical_pins - lhs_num_logical_pins;
-            int rhs_diff_num_pins = num_physical_pins - rhs_num_logical_pins;
+            int lhs_diff_num_pins = num_pins - lhs_num_logical_pins;
+            int rhs_diff_num_pins = num_pins - rhs_num_logical_pins;
 
             return lhs_diff_num_pins < rhs_diff_num_pins;
         };
@@ -4980,7 +4983,6 @@ static void link_physical_logical_types(std::vector<t_physical_tile_type>& Physi
             for (auto site : equivalent_sites) {
                 if (0 == strcmp(logical_block.name, site->pb_type->name)) {
                     logical_block.equivalent_tiles.push_back(&physical_tile);
-
                     break;
                 }
             }
@@ -5003,11 +5005,11 @@ static void link_physical_logical_types(std::vector<t_physical_tile_type>& Physi
         auto criteria = [&logical_block](const t_physical_tile_type* lhs, const t_physical_tile_type* rhs) {
             int num_logical_pins = logical_block.pb_type->num_pins;
 
-            int lhs_num_physical_pins = lhs->num_pins / lhs->capacity;
-            int rhs_num_physical_pins = rhs->num_pins / rhs->capacity;
+            int lhs_num_pins = lhs->num_inst_pins;
+            int rhs_num_pins = rhs->num_inst_pins;
 
-            int lhs_diff_num_pins = lhs_num_physical_pins - num_logical_pins;
-            int rhs_diff_num_pins = rhs_num_physical_pins - num_logical_pins;
+            int lhs_diff_num_pins = lhs_num_pins - num_logical_pins;
+            int rhs_diff_num_pins = rhs_num_pins - num_logical_pins;
 
             return lhs_diff_num_pins < rhs_diff_num_pins;
         };

vpr/src/place/compressed_grid.cpp

@@ -1,4 +1,5 @@
 #include "compressed_grid.h"
+#include "arch_util.h"
 #include "globals.h"
 
 std::vector<t_compressed_block_grid> create_compressed_block_grids() {
@@ -11,7 +12,9 @@ std::vector<t_compressed_block_grid> create_compressed_block_grids() {
         for (size_t y = 0; y < grid.height(); ++y) {
             const t_grid_tile& tile = grid[x][y];
             if (tile.width_offset == 0 && tile.height_offset == 0) {
-                for (auto& block : tile.type->equivalent_sites) {
+                auto equivalent_sites = get_equivalent_sites_set(tile.type);
+
+                for (auto& block : equivalent_sites) {
                     //Only record at block root location
                     block_locations[block->index].emplace_back(x, y);
                 }

vpr/src/place/move_utils.cpp

@@ -632,8 +632,8 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type,
 
     auto to_type = grid[to.x][to.y].type;
 
-    //Each x/y location contains only a single type, so we can pick a random
-    //z (capcity) location
+    //Each x/y location possibly contains multiple sub tiles, so we need to pick
+    //a z location within a compatible sub tile.
     to.z = vtr::irand(to_type->capacity - 1);
 
     VTR_ASSERT_MSG(is_tile_compatible(to_type, type), "Type must be compatible");

vpr/src/route/clock_connection_builders.cpp

@@ -1,6 +1,7 @@
 #include "clock_connection_builders.h"
 
 #include "globals.h"
+#include "arch_util.h"
 #include "rr_graph2.h"
 
 #include "vtr_assert.h"
@@ -264,7 +265,8 @@ void ClockToPinsConnection::create_switches(const ClockRRGraphBuilder& clock_gra
 
             // Ignore grid locations that do not have blocks
             bool has_pb_type = false;
-            for (auto logical_block : type->equivalent_sites) {
+            auto equivalent_sites = get_equivalent_sites_set(type);
+            for (auto logical_block : equivalent_sites) {
                 if (logical_block->pb_type) {
                     has_pb_type = true;
                     break;

vpr/src/util/vpr_utils.cpp

@@ -208,7 +208,7 @@ static std::tuple<int, int, int> get_pin_index_for_inst(t_physical_tile_type_ptr
 
         if (pin_index < total_pin_counts) {
             int pins_per_inst = sub_tile.num_phy_pins / sub_tile.capacity.total();
-            int inst_num = (pin_index - pin_offset) / sub_tile.capacity.total();
+            int inst_num = (pin_index - pin_offset) / pins_per_inst;
             int inst_index = (pin_index - pin_offset) % pins_per_inst;
 
             return std::make_tuple(inst_index, inst_num, sub_tile.index);
@@ -2067,6 +2067,7 @@ void print_switch_usage() {
  * }
  */
 
+// TODO FIX THIS!
 void place_sync_external_block_connections(ClusterBlockId iblk) {
     auto& cluster_ctx = g_vpr_ctx.clustering();
     auto& clb_nlist = cluster_ctx.clb_nlist;
@@ -2128,7 +2129,7 @@ t_physical_tile_type_ptr pick_best_physical_type(t_logical_block_type_ptr logica
 }
 
 t_logical_block_type_ptr pick_best_logical_type(t_physical_tile_type_ptr physical_tile) {
-    return physical_tile->equivalent_sites[0];
+    return physical_tile->sub_tiles[0].equivalent_sites[0];
 }
 
 t_physical_tile_type_ptr get_physical_tile_type(const ClusterBlockId blk) {