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update_arch: generate sub tiles in architecture files
Signed-off-by: Alessandro Comodi <[email protected]>
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vtr_flow/scripts/upgrade_arch.py

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Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@ def __init__(self):
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"add_missing_comb_model_internal_timing_edges",
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"add_tile_tags",
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"add_site_directs",
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"add_sub_tiles",
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]
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def parse_args():
@@ -150,6 +151,11 @@ def main():
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if result:
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modified = True
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if "add_sub_tiles" in args.features:
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result = add_sub_tiles(arch)
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if result:
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modified = True
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if modified:
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if args.debug:
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root.write(sys.stdout, pretty_print=args.pretty)
@@ -1025,5 +1031,76 @@ def add_site_directs(arch):
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return True
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def add_sub_tiles(arch):
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"""
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This function adds the sub tiles tags to the input architecture.
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Each physical tile must contain at least one sub tile.
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Note: the example below is only for explanatory reasons, the port/tile names are invented.
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BEFORE:
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<tiles>
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<tile name="BRAM_TILE" area="2" height="4" width="1" capacity="1">
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<inputs ... />
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<outputs ... />
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<fc ... />
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<pinlocations ... />
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<switchblock_locations ... />
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<equivalent_sites>
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<site pb_type="BRAM" pin_mapping="direct">
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</equivalent_sites>
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</tile>
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</tiles>
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AFTER:
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<tiles>
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<tile name="BRAM_TILE" area="2" height="4" width="1">
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<sub_tile name="BRAM_SUB_TILE_X" capacity="1">
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<inputs ... />
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<outputs ... />
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<fc ... />
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<pinlocations ... />
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<equivalent_sites>
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<site pb_type="BRAM" pin_mapping="direct">
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</equivalent_sites>
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</sub_tile>
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<switchblock_locations ... />
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</tile>
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</tiles>
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"""
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TAGS_TO_SWAP = ['fc', 'pinlocations', 'input', 'output', 'clock', 'equivalent_sites']
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def swap_tags(sub_tile, tile):
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# Moving tags from top level pb_type to tile
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for child in tile:
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if child.tag in TAGS_TO_SWAP:
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tile.remove(child)
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sub_tile.append(child)
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modified = False
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for tile in arch.iter('tile'):
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if tile.findall('./sub_tile'):
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continue
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sub_tile_name = tile.attrib['name']
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sub_tile = ET.Element('sub_tile', name='{}'.format(sub_tile_name))
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# Transfer capacity to sub tile
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if 'capacity' in tile.attrib.keys():
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sub_tile.attrib['capacity'] = tile.attrib['capacity']
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del tile.attrib['capacity']
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#Transfer tags to swap from tile to sub tile
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swap_tags(sub_tile, tile)
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tile.append(sub_tile)
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modified = True
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return modified
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if __name__ == "__main__":
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main()

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