Merge pull request #928 from verilog-to-routing/two_stage_routing

mustafabbas · web-flow · commit 7ffd6d4dd9aa · 2019-12-05T19:55:17.000-08:00
Clock Modeling: Added two Stage router
diff --git a/vpr/src/base/SetupVPR.cpp b/vpr/src/base/SetupVPR.cpp
@@ -342,6 +342,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts)
     RouterOpts->congested_routing_iteration_threshold_frac = Options.congested_routing_iteration_threshold_frac;
     RouterOpts->route_bb_update = Options.route_bb_update;
     RouterOpts->clock_modeling = Options.clock_modeling;
+    RouterOpts->two_stage_clock_routing = Options.two_stage_clock_routing;
     RouterOpts->high_fanout_threshold = Options.router_high_fanout_threshold;
     RouterOpts->router_debug_net = Options.router_debug_net;
     RouterOpts->router_debug_sink_rr = Options.router_debug_sink_rr;
diff --git a/vpr/src/base/read_options.cpp b/vpr/src/base/read_options.cpp
@@ -907,9 +907,7 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg
             "Specifies how constant nets (i.e. those driven to a constant\n"
             "value) are handled:\n"
             " * global: Treat constant nets as globals (not routed)\n"
-            " * route : Treat constant nets as normal nets (routed)\n"
-            " * dedicated_network : Build a dedicated clock network based on the\n"
-            "                       clock network specified in the architecture file\n")
+            " * route : Treat constant nets as normal nets (routed)\n")
         .default_value("global")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
@@ -919,10 +917,21 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg
             " * ideal: Treat clock pins as ideal\n"
             "          (i.e. no routing delays on clocks)\n"
             " * route: Treat the clock pins as normal nets\n"
-            "          (i.e. routed using inter-block routing)\n")
+            "          (i.e. routed using inter-block routing)\n"
+            " * dedicated_network : Build a dedicated clock network based on the\n"
+            "                       clock network specified in the architecture file\n")
         .default_value("ideal")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
+    gen_grp.add_argument<bool, ParseOnOff>(args.two_stage_clock_routing, "--two_stage_clock_routing")
+        .help(
+            "Routes clock nets in two stages if using a dedicated clock network.\n"
+            " * First stage: From the Net source to a dedicated clock network source\n"
+            " * Second stage: From the clock network source to net sinks\n")
+        .default_value("off")
+        .action(argparse::Action::STORE_TRUE)
+        .show_in(argparse::ShowIn::HELP_ONLY);
+
     gen_grp.add_argument<bool, ParseOnOff>(args.exit_before_pack, "--exit_before_pack")
         .help("Causes VPR to exit before packing starts (useful for statistics collection)")
         .default_value("off")
diff --git a/vpr/src/base/read_options.h b/vpr/src/base/read_options.h
@@ -56,6 +56,7 @@ struct t_options {
     argparse::ArgValue<float> target_device_utilization;
     argparse::ArgValue<e_constant_net_method> constant_net_method;
     argparse::ArgValue<e_clock_modeling> clock_modeling;
+    argparse::ArgValue<bool> two_stage_clock_routing;
     argparse::ArgValue<bool> exit_before_pack;
     argparse::ArgValue<bool> strict_checks;
     argparse::ArgValue<std::string> disable_errors;
diff --git a/vpr/src/base/vpr_api.cpp b/vpr/src/base/vpr_api.cpp
@@ -216,6 +216,7 @@ void vpr_init_with_options(const t_options* options, t_vpr_setup* vpr_setup, t_a
     vpr_setup->device_layout = options->device_layout;
     vpr_setup->constant_net_method = options->constant_net_method;
     vpr_setup->clock_modeling = options->clock_modeling;
+    vpr_setup->two_stage_clock_routing = options->two_stage_clock_routing;
     vpr_setup->exit_before_pack = options->exit_before_pack;
 
     VTR_LOG("\n");
diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h
@@ -162,6 +162,12 @@ struct DeviceContext : public Context {
     std::vector<std::unique_ptr<ClockNetwork>> clock_networks;
     std::vector<std::unique_ptr<ClockConnection>> clock_connections;
 
+    // rr_node idx that connects to the input of all clock network wires
+    // Useful for two stage clock routing
+    // XXX: currently only one place to source the clock networks so only storing
+    //      a single value
+    int virtual_clock_network_root_idx;
+
     /** Attributes for each rr_node.
      * key:     rr_node index
      * value:   map of <attribute_name, attribute_value>
diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h
@@ -939,6 +939,7 @@ struct t_router_opts {
     float congested_routing_iteration_threshold_frac;
     e_route_bb_update route_bb_update;
     enum e_clock_modeling clock_modeling; //How clock pins and nets should be handled
+    bool two_stage_clock_routing;         //How clock nets on dedicated networks should be routed
     int high_fanout_threshold;
     int router_debug_net;
     int router_debug_sink_rr;
@@ -1292,6 +1293,7 @@ struct t_vpr_setup {
     std::string device_layout;
     e_constant_net_method constant_net_method; //How constant nets should be handled
     e_clock_modeling clock_modeling;           //How clocks should be handled
+    bool two_stage_clock_routing;              //How clocks should be routed in the presence of a dedicated clock network
     bool exit_before_pack;                     //Exits early before starting packing (useful for collecting statistics without running/loading any stages)
 };
 
diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp
@@ -442,7 +442,8 @@ static bool check_adjacent(int from_node, int to_node) {
             } else if (to_type == CHANY) {
                 num_adj += chanx_chany_adjacent(from_node, to_node);
             } else {
-                VTR_ASSERT(0);
+                VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
+                                "in check_adjacent: %d and %d are not adjacent", from_node, to_node);
             }
             break;
 
@@ -473,7 +474,8 @@ static bool check_adjacent(int from_node, int to_node) {
             } else if (to_type == CHANX) {
                 num_adj += chanx_chany_adjacent(to_node, from_node);
             } else {
-                VTR_ASSERT(0);
+                VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
+                                "in check_adjacent: %d and %d are not adjacent", from_node, to_node);
             }
             break;
 
diff --git a/vpr/src/route/clock_connection_builders.cpp b/vpr/src/route/clock_connection_builders.cpp
@@ -49,6 +49,9 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
     auto& rr_nodes = device_ctx.rr_nodes;
     auto& rr_node_indices = device_ctx.rr_node_indices;
 
+    int virtual_clock_network_root_idx = create_virtual_clock_network_sink_node(switch_location.x, switch_location.y);
+    device_ctx.virtual_clock_network_root_idx = virtual_clock_network_root_idx;
+
     // rr_node indices for x and y channel routing wires and clock wires to connect to
     auto x_wire_indices = get_rr_node_chan_wires_at_location(
         rr_node_indices, CHANX, switch_location.x, switch_location.y);
@@ -73,9 +76,32 @@ void RoutingToClockConnection::create_switches(const ClockRRGraphBuilder& clock_
         for (size_t i = 0; i < num_wires_y; i++) {
             rr_nodes[y_wire_indices[i]].add_edge(clock_index, rr_switch_idx);
         }
+
+        // Connect to virtual clock sink node
+        // used by the two stage router
+        rr_nodes[clock_index].add_edge(virtual_clock_network_root_idx, rr_switch_idx);
     }
 }
 
+int RoutingToClockConnection::create_virtual_clock_network_sink_node(
+    int x,
+    int y) {
+    auto& device_ctx = g_vpr_ctx.mutable_device();
+    auto& rr_nodes = device_ctx.rr_nodes;
+    rr_nodes.emplace_back();
+    auto node_index = rr_nodes.size() - 1;
+
+    rr_nodes[node_index].set_coordinates(x, y, x, y);
+    rr_nodes[node_index].set_capacity(1);
+    rr_nodes[node_index].set_cost_index(SINK_COST_INDEX);
+    rr_nodes[node_index].set_type(SINK);
+    float R = 0.;
+    float C = 0.;
+    rr_nodes[node_index].set_rc_index(find_create_rr_rc_data(R, C));
+
+    return node_index;
+}
+
 /*
  * ClockToClockConneciton (setters)
  */
diff --git a/vpr/src/route/clock_connection_builders.h b/vpr/src/route/clock_connection_builders.h
@@ -54,6 +54,7 @@ class RoutingToClockConnection : public ClockConnection {
      */
     /* Connects the inter-block routing to the clock source at the specified coordinates */
     void create_switches(const ClockRRGraphBuilder& clock_graph);
+    int create_virtual_clock_network_sink_node(int x, int y);
 };
 
 class ClockToClockConneciton : public ClockConnection {
diff --git a/vpr/src/route/clock_network_builders.cpp b/vpr/src/route/clock_network_builders.cpp
@@ -274,8 +274,8 @@ int ClockRib::create_chanx_wire(int x_start,
     rr_nodes[node_index].set_type(CHANX);
     rr_nodes[node_index].set_capacity(1);
     rr_nodes[node_index].set_track_num(ptc_num);
-    auto rc_index = find_create_rr_rc_data(x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal);
-    rr_nodes[node_index].set_rc_index(rc_index);
+    rr_nodes[node_index].set_rc_index(find_create_rr_rc_data(
+        x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal));
     rr_nodes[node_index].set_direction(direction);
 
     short seg_index = 0;
@@ -523,8 +523,8 @@ int ClockSpine::create_chany_wire(int y_start,
     rr_nodes[node_index].set_type(CHANY);
     rr_nodes[node_index].set_capacity(1);
     rr_nodes[node_index].set_track_num(ptc_num);
-    auto rc_index = find_create_rr_rc_data(y_chan_wire.layer.r_metal, y_chan_wire.layer.c_metal);
-    rr_nodes[node_index].set_rc_index(rc_index);
+    rr_nodes[node_index].set_rc_index(find_create_rr_rc_data(
+        y_chan_wire.layer.r_metal, y_chan_wire.layer.c_metal));
     rr_nodes[node_index].set_direction(direction);
 
     short seg_index = 0;
diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp
@@ -799,6 +799,31 @@ void node_to_heap(int inode, float total_cost, int prev_node, int prev_edge, flo
     add_to_heap(hptr);
 }
 
+void drop_traceback_tail(ClusterNetId net_id) {
+    /* Removes the tail node from the routing traceback and updates
+     * it with the previous node from the traceback.
+     * This funtion is primarily called to remove the virtual clock
+     * sink from the routing traceback and replace it with the clock
+     * network root. */
+    auto& route_ctx = g_vpr_ctx.mutable_routing();
+
+    auto* tail_ptr = route_ctx.trace[net_id].tail;
+    auto node = tail_ptr->index;
+    route_ctx.trace_nodes[net_id].erase(node);
+    auto* trace_ptr = route_ctx.trace[net_id].head;
+    while (trace_ptr != nullptr) {
+        t_trace* next_ptr = trace_ptr->next;
+        if (next_ptr == tail_ptr) {
+            trace_ptr->iswitch = tail_ptr->iswitch;
+            trace_ptr->next = nullptr;
+            route_ctx.trace[net_id].tail = trace_ptr;
+            break;
+        }
+        trace_ptr = next_ptr;
+    }
+    free_trace_data(tail_ptr);
+}
+
 void free_traceback(ClusterNetId net_id) {
     /* Puts the entire traceback (old routing) for this net on the free list *
      * and sets the route_ctx.trace_head pointers etc. for the net to NULL.            */
diff --git a/vpr/src/route/route_common.h b/vpr/src/route/route_common.h
@@ -79,6 +79,7 @@ void node_to_heap(int inode, float cost, int prev_node, int prev_edge, float bac
 bool is_empty_heap();
 
 void free_traceback(ClusterNetId net_id);
+void drop_traceback_tail(ClusterNetId net_id);
 void free_traceback(t_trace* tptr);
 
 void add_to_mod_list(int inode, std::vector<int>& modified_rr_node_inf);
diff --git a/vpr/src/route/route_timing.cpp b/vpr/src/route/route_timing.cpp
diff --git a/vpr/src/route/rr_graph_area.cpp b/vpr/src/route/rr_graph_area.cpp
diff --git a/vpr/src/route/rr_node.cpp b/vpr/src/route/rr_node.cpp
diff --git a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_40nm.xml
diff --git a/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml b/vtr_flow/arch/timing/k6_frac_N10_frac_chain_mem32K_htree0_routedCLK_40nm.xml
