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SamuelHo10SamuelHo10
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fixed build issues and improved pair for loops
1 parent 81eba83 commit 700cc75

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4 files changed

+58
-71
lines changed

4 files changed

+58
-71
lines changed

‎libs/libarchfpga/src/arch_util.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1070,8 +1070,8 @@ const t_pin_to_pin_annotation* find_sequential_annotation(const t_pb_type* pb_ty
10701070
const t_pin_to_pin_annotation* annot = &pb_type->annotations[iannot];
10711071
InstPort annot_in(annot->input_pins);
10721072
if (annot_in.port_name() == port->name) {
1073-
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
1074-
if (annot->pairs[iprop].first == annot_type) {
1073+
for (const auto& [key, val] : annot->pairs) {
1074+
if (key == annot_type) {
10751075
return annot;
10761076
}
10771077
}
@@ -1089,9 +1089,9 @@ const t_pin_to_pin_annotation* find_combinational_annotation(const t_pb_type* pb
10891089
for (const auto& annot_out_str : vtr::split(annot->output_pins)) {
10901090
InstPort out_pins(annot_out_str);
10911091
if (in_pins.port_name() == in_port && out_pins.port_name() == out_port) {
1092-
for (size_t iprop = 0; iprop < annot->pairs.size(); ++iprop) {
1093-
if (annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX
1094-
|| annot->pairs[iprop].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
1092+
for (const auto& [key, val] : annot->pairs) {
1093+
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
1094+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN) {
10951095
return annot;
10961096
}
10971097
}

‎libs/libarchfpga/src/physical_types.h

Lines changed: 33 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -420,13 +420,13 @@ struct t_clock_network {
420420
float dens; /* Switching density of net assigned to this clock */
421421
float period; /* Period of clock */
422422

423-
t_clock_network(){
424-
autosize_buffer = false;
425-
buffer_size = 0.0f;
426-
C_wire = 0.0f;
427-
prob = 0.0f;
428-
dens = 0.0f;
429-
period = 0.0f;
423+
t_clock_network() {
424+
autosize_buffer = false;
425+
buffer_size = 0.0f;
426+
C_wire = 0.0f;
427+
prob = 0.0f;
428+
dens = 0.0f;
429+
period = 0.0f;
430430
}
431431
};
432432

@@ -442,7 +442,7 @@ struct t_power_arch {
442442
float LUT_transistor_size;
443443

444444
t_power_arch() {
445-
C_wire_local = 0.0f;
445+
C_wire_local = 0.0f;
446446
logical_effort_factor = 0.0f;
447447
local_interc_factor = 0.0f;
448448
transistors_per_SRAM_bit = 0.0f;
@@ -456,7 +456,7 @@ struct t_power_arch {
456456
struct t_power_usage {
457457
float dynamic;
458458
float leakage;
459-
t_power_usage(){
459+
t_power_usage() {
460460
dynamic = 0.0f;
461461
leakage = 0.0f;
462462
}
@@ -487,17 +487,14 @@ struct t_class {
487487

488488
/* Struct to hold the class ranges for specific sub tiles */
489489
struct t_class_range {
490-
int low;
491-
int high;
490+
int low = 0;
491+
int high = 0;
492492
// Returns the total number of classes
493493
int total_num() const {
494494
return high - low + 1;
495495
}
496496

497-
t_class_range(){
498-
low = 0;
499-
high = 0;
500-
}
497+
t_class_range() = default;
501498

502499
t_class_range(int low_class_num, int high_class_num)
503500
: low(low_class_num)
@@ -506,17 +503,14 @@ struct t_class_range {
506503

507504
// Struct to hold the pin ranges for a specific sub block
508505
struct t_pin_range {
509-
int low;
510-
int high;
506+
int low = 0;
507+
int high = 0;
511508
// Returns the total number of pins
512509
int total_num() const {
513510
return high - low + 1;
514511
}
515512

516-
t_pin_range(){
517-
low = 0;
518-
high = 0;
519-
}
513+
t_pin_range() = default;
520514

521515
t_pin_range(int low_class_num, int high_class_num)
522516
: low(low_class_num)
@@ -561,10 +555,10 @@ struct t_port_power {
561555
int scaled_by_port_pin_idx;
562556
bool reverse_scaled; /* Scale by (1-prob) */
563557

564-
t_port_power(){
565-
wire_type = (e_power_wire_type) 0;
558+
t_port_power() {
559+
wire_type = (e_power_wire_type)0;
566560
wire = {0.0f}; // Default to C = 0.0f
567-
buffer_type = (e_power_buffer_type) 0;
561+
buffer_type = (e_power_buffer_type)0;
568562
buffer_size = 0.0f;
569563
pin_toggle_initialized = false;
570564
energy_per_toggle = 0.0f;
@@ -903,15 +897,11 @@ struct t_physical_pin {
903897
* above the base die, the layer_num is 1 and so on.
904898
*/
905899
struct t_physical_tile_loc {
906-
int x;
907-
int y;
908-
int layer_num;
909-
910-
t_physical_tile_loc(){
911-
x = OPEN;
912-
y = OPEN;
913-
layer_num = OPEN;
914-
}
900+
int x = OPEN;
901+
int y = OPEN;
902+
int layer_num = OPEN;
903+
904+
t_physical_tile_loc() = default;
915905

916906
t_physical_tile_loc(int x_val, int y_val, int layer_num_val)
917907
: x(x_val)
@@ -1202,8 +1192,8 @@ struct t_interconnect {
12021192
t_interconnect_power* interconnect_power;
12031193
t_metadata_dict meta;
12041194

1205-
t_interconnect(){
1206-
type = (e_interconnect) 0;
1195+
t_interconnect() {
1196+
type = (e_interconnect)0;
12071197
name = nullptr;
12081198
input_string = nullptr;
12091199
output_string = nullptr;
@@ -1254,14 +1244,14 @@ struct t_port {
12541244

12551245
t_port_power* port_power;
12561246

1257-
t_port(){
1247+
t_port() {
12581248
name = nullptr;
12591249
model_port = nullptr;
1260-
type = (PORTS) 0;
1250+
type = (PORTS)0;
12611251
is_clock = false;
12621252
is_non_clock_global = false;
12631253
num_pins = 0;
1264-
equivalent = (PortEquivalence) 0;
1254+
equivalent = (PortEquivalence)0;
12651255
parent_pb_type = nullptr;
12661256
port_class = nullptr;
12671257
index = 0;
@@ -1350,8 +1340,8 @@ struct t_pin_to_pin_annotation {
13501340
clock = nullptr;
13511341

13521342
line_num = 0;
1353-
type = (e_pin_to_pin_annotation_type) 0;
1354-
format = (e_pin_to_pin_annotation_format) 0;
1343+
type = (e_pin_to_pin_annotation_type)0;
1344+
format = (e_pin_to_pin_annotation_format)0;
13551345
}
13561346
};
13571347

@@ -2125,18 +2115,15 @@ struct t_wireconn_inf {
21252115
class SB_Side_Connection {
21262116
public:
21272117
/* specify the two SB sides that form a connection */
2128-
enum e_side from_side;
2129-
enum e_side to_side;
2118+
enum e_side from_side = TOP;
2119+
enum e_side to_side = TOP;
21302120

21312121
void set_sides(enum e_side from, enum e_side to) {
21322122
from_side = from;
21332123
to_side = to;
21342124
}
21352125

2136-
SB_Side_Connection(){
2137-
from_side = TOP;
2138-
to_side = TOP;
2139-
}
2126+
SB_Side_Connection() = default;
21402127

21412128
SB_Side_Connection(enum e_side from, enum e_side to)
21422129
: from_side(from)

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -245,7 +245,7 @@ static t_pin_to_pin_annotation get_pack_pattern(std::string pp_name, std::string
245245

246246
pp.type = E_ANNOT_PIN_TO_PIN_PACK_PATTERN;
247247
pp.format = E_ANNOT_PIN_TO_PIN_CONSTANT;
248-
pp.pairs.push_back(std::make_pair(E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name));
248+
pp.pairs.push_back({E_ANNOT_PIN_TO_PIN_PACK_PATTERN_NAME, pp_name});
249249
pp.input_pins = vtr::strdup(input.c_str());
250250
pp.output_pins = vtr::strdup(output.c_str());
251251

‎vpr/src/pack/pb_type_graph_annotations.cpp

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,7 @@ static void inferr_unspecified_pb_graph_edge_delays(t_pb_graph_edge* pb_graph_pi
4040
static t_pb_graph_pin* find_clock_pin(t_pb_graph_node* gnode, const char* clock, int line_num);
4141

4242
void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
43-
int i, j, k, m;
43+
int i, j, k;
4444
const t_pb_type* pb_type;
4545
t_pin_to_pin_annotation* annotations;
4646

@@ -51,19 +51,19 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
5151
annotations = pb_type->annotations;
5252
for (i = 0; i < pb_type->num_annotations; i++) {
5353
if (annotations[i].type == E_ANNOT_PIN_TO_PIN_DELAY) {
54-
for (j = 0; j < static_cast<int>(annotations[i].pairs.size()); j++) {
55-
if (annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX
56-
|| annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN
57-
|| annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX
58-
|| annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN
59-
|| annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP
60-
|| annotations[i].pairs[j].first == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) {
54+
for (const auto& [key, val] : annotations[i].pairs) {
55+
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
56+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN
57+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX
58+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN
59+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP
60+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) {
6161
load_delay_annotations(annotations[i].line_num, pb_graph_node, OPEN,
62-
annotations[i].format, (enum e_pin_to_pin_delay_annotations)annotations[i].pairs[j].first,
62+
annotations[i].format, (enum e_pin_to_pin_delay_annotations)key,
6363
annotations[i].input_pins,
6464
annotations[i].output_pins,
6565
annotations[i].clock,
66-
annotations[i].pairs[j].second.c_str());
66+
val.c_str());
6767
} else {
6868
VTR_ASSERT(false);
6969
}
@@ -77,20 +77,20 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) {
7777
annotations = pb_type->modes[i].interconnect[j].annotations;
7878
for (k = 0; k < pb_type->modes[i].interconnect[j].num_annotations; k++) {
7979
if (annotations[k].type == E_ANNOT_PIN_TO_PIN_DELAY) {
80-
for (m = 0; m < static_cast<int>(annotations[k].pairs.size()); m++) {
81-
if (annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_MAX
82-
|| annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_MIN
83-
|| annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX
84-
|| annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN
85-
|| annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP
86-
|| annotations[k].pairs[m].first == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) {
80+
for (const auto& [key, val] : annotations[k].pairs) {
81+
if (key == E_ANNOT_PIN_TO_PIN_DELAY_MAX
82+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_MIN
83+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MAX
84+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN
85+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP
86+
|| key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) {
8787
load_delay_annotations(annotations[k].line_num, pb_graph_node, i,
8888
annotations[k].format,
89-
(enum e_pin_to_pin_delay_annotations)annotations[k].pairs[m].first,
89+
(enum e_pin_to_pin_delay_annotations)key,
9090
annotations[k].input_pins,
9191
annotations[k].output_pins,
9292
annotations[k].clock,
93-
annotations[k].pairs[m].second.c_str());
93+
val.c_str());
9494
} else {
9595
VTR_ASSERT(false);
9696
}

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