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added default constructors
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1 file changed

+110
-26
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libs/libarchfpga/src/physical_types.h

Lines changed: 110 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -420,7 +420,14 @@ struct t_clock_network {
420420
float dens; /* Switching density of net assigned to this clock */
421421
float period; /* Period of clock */
422422

423-
t_clock_network() = default;
423+
t_clock_network(){
424+
autosize_buffer = false;
425+
buffer_size = 0.0f;
426+
C_wire = 0.0f;
427+
prob = 0.0f;
428+
dens = 0.0f;
429+
period = 0.0f;
430+
}
424431
};
425432

426433
/* Power-related architecture information */
@@ -433,12 +440,26 @@ struct t_power_arch {
433440
float mux_transistor_size;
434441
float FF_size;
435442
float LUT_transistor_size;
443+
444+
t_power_arch() {
445+
C_wire_local = 0.0f;
446+
logical_effort_factor = 0.0f;
447+
local_interc_factor = 0.0f;
448+
transistors_per_SRAM_bit = 0.0f;
449+
mux_transistor_size = 0.0f;
450+
FF_size = 0.0f;
451+
LUT_transistor_size = 0.0f;
452+
}
436453
};
437454

438455
/* Power usage for an entity */
439456
struct t_power_usage {
440457
float dynamic;
441458
float leakage;
459+
t_power_usage(){
460+
dynamic = 0.0f;
461+
leakage = 0.0f;
462+
}
442463
};
443464

444465
/*************************************************************************************************/
@@ -466,14 +487,17 @@ struct t_class {
466487

467488
/* Struct to hold the class ranges for specific sub tiles */
468489
struct t_class_range {
469-
int low = 0;
470-
int high = 0;
490+
int low;
491+
int high;
471492
// Returns the total number of classes
472493
int total_num() const {
473494
return high - low + 1;
474495
}
475496

476-
t_class_range() = default;
497+
t_class_range(){
498+
low = 0;
499+
high = 0;
500+
}
477501

478502
t_class_range(int low_class_num, int high_class_num)
479503
: low(low_class_num)
@@ -482,14 +506,17 @@ struct t_class_range {
482506

483507
// Struct to hold the pin ranges for a specific sub block
484508
struct t_pin_range {
485-
int low = 0;
486-
int high = 0;
509+
int low;
510+
int high;
487511
// Returns the total number of pins
488512
int total_num() const {
489513
return high - low + 1;
490514
}
491515

492-
t_pin_range() = default;
516+
t_pin_range(){
517+
low = 0;
518+
high = 0;
519+
}
493520

494521
t_pin_range(int low_class_num, int high_class_num)
495522
: low(low_class_num)
@@ -533,6 +560,18 @@ struct t_port_power {
533560
t_port* scaled_by_port;
534561
int scaled_by_port_pin_idx;
535562
bool reverse_scaled; /* Scale by (1-prob) */
563+
564+
t_port_power(){
565+
wire_type = (e_power_wire_type) 0;
566+
wire = {0.0f}; // Default to C = 0.0f
567+
buffer_type = (e_power_buffer_type) 0;
568+
buffer_size = 0.0f;
569+
pin_toggle_initialized = false;
570+
energy_per_toggle = 0.0f;
571+
scaled_by_port = nullptr;
572+
scaled_by_port_pin_idx = 0;
573+
reverse_scaled = false;
574+
}
536575
};
537576

538577
/**
@@ -864,11 +903,15 @@ struct t_physical_pin {
864903
* above the base die, the layer_num is 1 and so on.
865904
*/
866905
struct t_physical_tile_loc {
867-
int x = OPEN;
868-
int y = OPEN;
869-
int layer_num = OPEN;
870-
871-
t_physical_tile_loc() = default;
906+
int x;
907+
int y;
908+
int layer_num;
909+
910+
t_physical_tile_loc(){
911+
x = OPEN;
912+
y = OPEN;
913+
layer_num = OPEN;
914+
}
872915

873916
t_physical_tile_loc(int x_val, int y_val, int layer_num_val)
874917
: x(x_val)
@@ -1140,26 +1183,39 @@ struct t_mode {
11401183
*/
11411184
struct t_interconnect {
11421185
enum e_interconnect type;
1143-
char* name = nullptr;
1186+
char* name;
11441187

1145-
char* input_string = nullptr;
1146-
char* output_string = nullptr;
1188+
char* input_string;
1189+
char* output_string;
11471190

1148-
t_pin_to_pin_annotation* annotations = nullptr; /* [0..num_annotations-1] */
1149-
int num_annotations = 0;
1150-
bool infer_annotations = false;
1191+
t_pin_to_pin_annotation* annotations; /* [0..num_annotations-1] */
1192+
int num_annotations;
1193+
bool infer_annotations;
11511194

1152-
int line_num = 0; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */
1195+
int line_num; /* Interconnect is processed later, need to know what line number it messed up on to give proper error message */
11531196

1154-
int parent_mode_index = 0;
1197+
int parent_mode_index;
11551198

11561199
/* Power related members */
1157-
t_mode* parent_mode = nullptr;
1200+
t_mode* parent_mode;
11581201

1159-
t_interconnect_power* interconnect_power = nullptr;
1202+
t_interconnect_power* interconnect_power;
11601203
t_metadata_dict meta;
11611204

1162-
t_interconnect() = default;
1205+
t_interconnect(){
1206+
type = (e_interconnect) 0;
1207+
name = nullptr;
1208+
input_string = nullptr;
1209+
output_string = nullptr;
1210+
annotations = nullptr;
1211+
num_annotations = 0;
1212+
infer_annotations = false;
1213+
line_num = 0;
1214+
parent_mode_index = 0;
1215+
parent_mode = nullptr;
1216+
interconnect_power = nullptr;
1217+
meta = t_metadata_dict();
1218+
}
11631219
};
11641220

11651221
/** Describes I/O and clock ports
@@ -1197,6 +1253,22 @@ struct t_port {
11971253
int absolute_first_pin_index;
11981254

11991255
t_port_power* port_power;
1256+
1257+
t_port(){
1258+
name = nullptr;
1259+
model_port = nullptr;
1260+
type = (PORTS) 0;
1261+
is_clock = false;
1262+
is_non_clock_global = false;
1263+
num_pins = 0;
1264+
equivalent = (PortEquivalence) 0;
1265+
parent_pb_type = nullptr;
1266+
port_class = nullptr;
1267+
index = 0;
1268+
port_index_by_type = 0;
1269+
absolute_first_pin_index = 0;
1270+
port_power = nullptr;
1271+
}
12001272
};
12011273

12021274
struct t_pb_type_power {
@@ -1223,6 +1295,15 @@ struct t_interconnect_power {
12231295
int num_output_ports;
12241296
int num_pins_per_port;
12251297
float transistor_cnt;
1298+
1299+
t_interconnect_power() {
1300+
power_usage = t_power_usage();
1301+
port_info_initialized = false;
1302+
num_input_ports = 0;
1303+
num_output_ports = 0;
1304+
num_pins_per_port = 0;
1305+
transistor_cnt = 0.0f;
1306+
}
12261307
};
12271308

12281309
struct t_interconnect_pins {
@@ -2044,15 +2125,18 @@ struct t_wireconn_inf {
20442125
class SB_Side_Connection {
20452126
public:
20462127
/* specify the two SB sides that form a connection */
2047-
enum e_side from_side = TOP;
2048-
enum e_side to_side = TOP;
2128+
enum e_side from_side;
2129+
enum e_side to_side;
20492130

20502131
void set_sides(enum e_side from, enum e_side to) {
20512132
from_side = from;
20522133
to_side = to;
20532134
}
20542135

2055-
SB_Side_Connection() = default;
2136+
SB_Side_Connection(){
2137+
from_side = TOP;
2138+
to_side = TOP;
2139+
}
20562140

20572141
SB_Side_Connection(enum e_side from, enum e_side to)
20582142
: from_side(from)

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