vpr: rename gen_post_synthesis_netlist to gen_post_implementation_merged_netlist

Signed-off-by: Paweł Czarnecki <[email protected]>

Author: lpawelcz

doc/src/vpr/command_line_usage.rst

@@ -1254,11 +1254,11 @@ Analysis Options
 
     **Default:** ``off``
 
-.. option:: --gen_post_synthesis_merged_netlist { on | off }
+.. option:: --gen_post_implementation_merged_netlist { on | off }
 
     This option is based on ``--gen_post_synthesis_netlist``.
-    The difference is that ``--gen_post_synthesis_merged_netlist`` generates only single verilog file with merged top module multi-bit ports of the implemented circuit.
-    The name of the file is ``<basename>_merged_post_synthesis.v``
+    The difference is that ``--gen_post_implementation_merged_netlist`` generates only single verilog file with merged top module multi-bit ports of the implemented circuit.
+    The name of the file is ``<basename>_merged_post_implementation.v``
 
     **Default:** ``off``
 

vpr/src/base/SetupVPR.cpp

@@ -623,7 +623,7 @@ static void SetupAnalysisOpts(const t_options& Options, t_analysis_opts& analysi
     }
 
     analysis_opts.gen_post_synthesis_netlist = Options.Generate_Post_Synthesis_Netlist;
-    analysis_opts.gen_post_synthesis_merged_netlist = Options.Generate_Post_Synthesis_Merged_Netlist;
+    analysis_opts.gen_post_implementation_merged_netlist = Options.Generate_Post_Implementation_Merged_Netlist;
 
     analysis_opts.timing_report_npaths = Options.timing_report_npaths;
     analysis_opts.timing_report_detail = Options.timing_report_detail;

vpr/src/base/netlist_writer.cpp

@@ -2121,7 +2121,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
 };
 
 /**
- * @brief A class which writes post-synthesis merged netlists (Verilog)
+ * @brief A class which writes post-implementation merged netlists (Verilog)
  *
  * It implements the NetlistVisitor interface used by NetlistWalker (see netlist_walker.h)
  */
@@ -2328,7 +2328,7 @@ void netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDe
 
 ///@brief Main routing for this file. See netlist_writer.h for details.
 void merged_netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDelayCalculator> delay_calc, struct t_analysis_opts opts) {
-    std::string verilog_filename = basename + "_merged_post_synthesis.v";
+    std::string verilog_filename = basename + "_merged_post_implementation.v";
 
     VTR_LOG("Writing Implementation Netlist: %s\n", verilog_filename.c_str());
 

vpr/src/base/netlist_writer.h

@@ -18,10 +18,10 @@
 void netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDelayCalculator> delay_calc, struct t_analysis_opts opts);
 
 /**
- * @brief Writes out the post-synthesis implementation netlists in Verilog format.
+ * @brief Writes out the post implementation netlist in Verilog format.
  *        It has its top module ports merged into multi-bit ones.
  *
- * Written filename ends in {basename}_merged_post_synthesis.v where {basename} is the
+ * Written filename ends in {basename}_merged_post_implementation.v where {basename} is the
  * basename argument.
  */
 void merged_netlist_writer(const std::string basename, std::shared_ptr<const AnalysisDelayCalculator> delay_calc, struct t_analysis_opts opts);

vpr/src/base/read_options.cpp

@@ -2532,9 +2532,9 @@ argparse::ArgumentParser create_arg_parser(std::string prog_name, t_options& arg
         .default_value("off")
         .show_in(argparse::ShowIn::HELP_ONLY);
 
-    analysis_grp.add_argument<bool, ParseOnOff>(args.Generate_Post_Synthesis_Merged_Netlist, "--gen_post_synthesis_merged_netlist")
+    analysis_grp.add_argument<bool, ParseOnOff>(args.Generate_Post_Implementation_Merged_Netlist, "--gen_post_implementation_merged_netlist")
         .help(
-            "Generates the post-synthesis netlist with merged top module ports"
+            "Generates the post-implementation netlist with merged top module ports"
             " Used for post-implementation simulation and verification")
         .default_value("off")
         .show_in(argparse::ShowIn::HELP_ONLY);

vpr/src/base/read_options.h

@@ -208,7 +208,7 @@ struct t_options {
     /* Analysis options */
     argparse::ArgValue<bool> full_stats;
     argparse::ArgValue<bool> Generate_Post_Synthesis_Netlist;
-    argparse::ArgValue<bool> Generate_Post_Synthesis_Merged_Netlist;
+    argparse::ArgValue<bool> Generate_Post_Implementation_Merged_Netlist;
     argparse::ArgValue<int> timing_report_npaths;
     argparse::ArgValue<e_timing_report_detail> timing_report_detail;
     argparse::ArgValue<bool> timing_report_skew;

vpr/src/base/vpr_api.cpp

@@ -1282,8 +1282,8 @@ void vpr_analysis(t_vpr_setup& vpr_setup, const t_arch& Arch, const RouteStatus&
                            vpr_setup.AnalysisOpts);
         }
 
-        //Write the post-syntesis merged netlist
-        if (vpr_setup.AnalysisOpts.gen_post_synthesis_merged_netlist) {
+        //Write the post-implementation merged netlist
+        if (vpr_setup.AnalysisOpts.gen_post_implementation_merged_netlist) {
             merged_netlist_writer(atom_ctx.nlist.netlist_name().c_str(), analysis_delay_calc, vpr_setup.AnalysisOpts);
         }
 

vpr/src/base/vpr_types.h

@@ -1256,7 +1256,7 @@ struct t_analysis_opts {
     e_stage_action doAnalysis;
 
     bool gen_post_synthesis_netlist;
-    bool gen_post_synthesis_merged_netlist;
+    bool gen_post_implementation_merged_netlist;
     e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_input_handling;
     e_post_synth_netlist_unconn_handling post_synth_netlist_unconn_output_handling;