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vpr: base: netlist writer: change formatting
Signed-off-by: Paweł Czarnecki <[email protected]>
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vpr/src/base/netlist_writer.cpp

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2439,8 +2439,6 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
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//Pins
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if (nets.size() == 1) {
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//Single-bit port
2442-
//Port name
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os << indent(depth) << "." << port_name << "(";
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if (nets[0].empty()) {
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//Disconnected
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if (type == PortType::INPUT || type == PortType::CLOCK) {
@@ -2453,7 +2451,6 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
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//Connected
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os << escape_verilog_identifier(nets[0]);
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}
2456-
os << ")";
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} else {
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// Check if all pins are unconnected
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bool all_unconnected = true;
@@ -2473,8 +2470,7 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
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os << "{"
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<< "\n";
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for (int ipin = (int)nets.size() - 1; ipin >= 0; --ipin) { //Reverse order to match endianess
2476-
std::string name = port_name + "[" + std::to_string(ipin) + "]";
2477-
os << indent(depth) << "." << escape_verilog_identifier(name) << " (";
2473+
os << indent(depth + 1);
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if (nets[ipin].empty()) {
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//Disconnected
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if (type == PortType::INPUT || type == PortType::CLOCK) {
@@ -2498,6 +2494,7 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
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os << indent(depth) + " }";
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}
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}
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os << ")";
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}
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///@brief Escapes the given identifier to be safe for verilog

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