Skip to content

Commit 6aa1d56

Browse files
sdamghansdamghan
authored
Merge pull request #1953 from sdamghan/fix_yosys_odin_dsp
Fix DSP blocks synthesis bug in Yosys+Odin-II
2 parents 6e5cc6a + 5192448 commit 6aa1d56

21 files changed

+437
-53
lines changed

‎ODIN_II/SRC/BLIFElaborate.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -301,6 +301,7 @@ void blif_elaborate_node(nnode_t* node, short traverse_number, netlist_t* netlis
301301
case PAD_NODE: //fallthrough
302302
case INPUT_NODE: //fallthrough
303303
case OUTPUT_NODE: //fallthrough
304+
case HARD_IP: //fallthrough
304305
case BUF_NODE: //fallthrough
305306
case BITWISE_NOT: //fallthrough
306307
case BITWISE_AND: //fallthrough
@@ -312,7 +313,6 @@ void blif_elaborate_node(nnode_t* node, short traverse_number, netlist_t* netlis
312313
/* some are already resolved for this phase */
313314
break;
314315
}
315-
case HARD_IP:
316316
case ADDER_FUNC:
317317
case CARRY_FUNC:
318318
case CLOCK_NODE:

‎ODIN_II/SRC/BLIFReader.cpp

Lines changed: 22 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -349,31 +349,36 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
349349
char* subcircuit_stripped_name = get_stripped_name(subcircuit_name);
350350
/* check for coarse-grain configuration */
351351
if (configuration.coarsen) {
352-
new_node->type = yosys_subckt_strmap[subcircuit_name];
352+
if (yosys_subckt_strmap.find(subcircuit_name) != yosys_subckt_strmap.end())
353+
new_node->type = yosys_subckt_strmap[subcircuit_name];
353354

354-
if (subcircuit_stripped_name && new_node->type == NO_OP)
355+
if (new_node->type == NO_OP && yosys_subckt_strmap.find(subcircuit_stripped_name) != yosys_subckt_strmap.end())
355356
new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
356357

357358
if (new_node->type == NO_OP) {
358359
char new_name[READ_BLIF_BUFFER];
359360
vtr::free(new_node->name);
360361
/* in case of weird names, need to add memories manually */
361-
if (ports->count == 5) {
362+
int sc_spot = -1;
363+
char* yosys_subckt_str = NULL;
364+
if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
362365
/* specify node type */
363-
new_node->type = yosys_subckt_strmap[SINGLE_PORT_RAM_string];
366+
new_node->type = yosys_subckt_strmap[yosys_subckt_str];
364367
/* specify node name */
365-
odin_sprintf(new_name, "\\%s~%ld", SINGLE_PORT_RAM_string, hard_block_number - 1);
366-
new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
367-
} else if (ports->count == 9) {
368+
odin_sprintf(new_name, "\\%s~%ld", yosys_subckt_str, hard_block_number - 1);
369+
} else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
368370
/* specify node type */
369-
new_node->type = yosys_subckt_strmap[DUAL_PORT_RAM_string];
371+
new_node->type = HARD_IP;
370372
/* specify node name */
371-
odin_sprintf(new_name, "\\%s~%ld", DUAL_PORT_RAM_string, hard_block_number - 1);
372-
new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
373+
odin_sprintf(new_name, "\\%s~%ld", subcircuit_stripped_name, hard_block_number - 1);
373374
} else {
374375
error_message(PARSE_BLIF, unknown_location,
375-
"Unsupported sub-circuit type (%s) in BLIF file.\n", subcircuit_name);
376+
"Unsupported subcircuit type (%s) in BLIF file.\n", subcircuit_name);
376377
}
378+
new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
379+
380+
// CLEAN UP
381+
vtr::free(yosys_subckt_str);
377382
}
378383

379384
if (new_node->type == BRAM) {
@@ -410,7 +415,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
410415

411416
if (!model)
412417
error_message(PARSE_BLIF, unknown_location,
413-
"Failed to retrieve sub-circuit model (%s)\n", subcircuit_name);
418+
"Failed to retrieve subcircuit model (%s)\n", subcircuit_name);
414419

415420
/* Add input and output ports to the new node. */
416421
else {
@@ -481,7 +486,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
481486
}
482487

483488
// Create a fake ast node.
484-
if (!configuration.coarsen) {
489+
if (!configuration.coarsen || new_node->type == HARD_IP) {
485490
new_node->related_ast_node = create_node_w_type(HARD_BLOCK, my_location);
486491
new_node->related_ast_node->children = (ast_node_t**)vtr::calloc(1, sizeof(ast_node_t*));
487492
new_node->related_ast_node->identifier_node = create_tree_node_id(vtr::strdup(subcircuit_name), my_location);
@@ -2147,8 +2152,11 @@ void BLIF::Reader::hard_block_sensitivities(const char* subckt_name, nnode_t* ne
21472152
char* ptr;
21482153
char* buffer = NULL;
21492154
attr_t* attributes = new_node->attributes;
2155+
operation_list op = (yosys_subckt_strmap.find(subckt_name) != yosys_subckt_strmap.end())
2156+
? yosys_subckt_strmap[subckt_name]
2157+
: NO_OP;
21502158

2151-
if (need_params(yosys_subckt_strmap[subckt_name])) {
2159+
if (need_params(op)) {
21522160
while (getbline(buffer, READ_BLIF_BUFFER, file)) {
21532161
my_location.line += 1;
21542162
ptr = vtr::strtok(buffer, TOKENS, file, buffer);

‎ODIN_II/SRC/BLIFWriter.cpp

Lines changed: 9 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,8 +74,15 @@ inline void BLIF::Writer::_write(const netlist_t* netlist) {
7474
output_blif(this->output_file, netlist);
7575
}
7676

77-
inline void BLIF::Writer::_create_file(const file_type_e /* file_type */) {
78-
this->output_file = create_blif(global_args.output_file.value().c_str());
77+
inline void BLIF::Writer::_create_file(const char* file_name, const file_type_e file_type) {
78+
// validate the file_name pionter
79+
oassert(file_name);
80+
// validate the file type
81+
if (file_type != _BLIF)
82+
error_message(UTIL, unknown_location,
83+
"BLIF back-end entity cannot create file types(%d) other than BLIF", file_type);
84+
// create the BLIF file and set it as the output file
85+
this->output_file = create_blif(file_name);
7986
}
8087
/**
8188
* ---------------------------------------------------------------------------------------------

‎ODIN_II/SRC/GenericIO.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ void GenericIO::_write(const netlist_t* /* netlist */) {
4444
"Function \"%s\" is called for reading the input file without definition provided!\n", __PRETTY_FUNCTION__);
4545
}
4646

47-
void GenericIO::_create_file(const file_type_e /* file_type */) {
47+
void GenericIO::_create_file(const char* /* file_name */, const file_type_e /* file_type */) {
4848
error_message(UTIL, unknown_location,
4949
"Function \"%s\" is called for reading the input file without definition provided!\n", __PRETTY_FUNCTION__);
5050
}

‎ODIN_II/SRC/GenericWriter.cpp

Lines changed: 22 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -37,13 +37,16 @@ GenericWriter::GenericWriter()
3737
: GenericIO() {
3838
this->output_file = NULL;
3939
this->blif_writer = NULL;
40+
this->verilog_writer = NULL;
4041
}
4142

4243
GenericWriter::~GenericWriter() {
4344
if (this->output_file)
4445
fclose(this->output_file);
4546
if (this->blif_writer)
4647
delete this->blif_writer;
48+
if (this->verilog_writer)
49+
delete this->verilog_writer;
4750
}
4851

4952
inline void GenericWriter::_write(const netlist_t* netlist) {
@@ -52,12 +55,12 @@ inline void GenericWriter::_write(const netlist_t* netlist) {
5255
this->write_blif(netlist);
5356
break;
5457
}
58+
case (file_type_e::_VERILOG): {
59+
this->write_verilog(netlist);
60+
break;
61+
}
5562
/**
5663
* [TODO]
57-
* case (file_type_e::_VERILOG): {
58-
* netlist = this->write_verilog();
59-
* break;
60-
* }
6164
* case (file_type_e::_EBLIF): {
6265
* netlist = this->write_verilog();
6366
* break;
@@ -79,22 +82,30 @@ inline void GenericWriter::write_blif(const netlist_t* netlist) {
7982
this->blif_writer->_write(netlist);
8083
}
8184

82-
inline void GenericWriter::_create_file(const file_type_e file_type) {
85+
inline void GenericWriter::write_verilog(const netlist_t* netlist) {
86+
oassert(this->verilog_writer);
87+
this->verilog_writer->_write(netlist);
88+
}
89+
90+
inline void GenericWriter::_create_file(const char* file_name, const file_type_e file_type) {
91+
// validate the file_name pointer
92+
oassert(file_name);
93+
8394
switch (file_type) {
8495
case (file_type_e::_BLIF): {
8596
if (!this->blif_writer) {
8697
this->blif_writer = new BLIF::Writer();
87-
this->blif_writer->_create_file(file_type);
98+
this->blif_writer->_create_file(file_name, file_type);
8899
}
89100
break;
90101
}
102+
case (file_type_e::_VERILOG): {
103+
this->verilog_writer = new Verilog::Writer();
104+
this->verilog_writer->_create_file(file_name, file_type);
105+
break;
106+
}
91107
/**
92108
* [TODO]
93-
* case (file_type_e::_VERILOG): {
94-
* this->verilog_writer = new VERILOG::Writer();
95-
* this->verilog_writer->_create_file();
96-
* break;
97-
* }
98109
* case (file_type_e::_EBLIF): {
99110
* this->eblif_writer = new EBLIF::Writer();
100111
* this->eblif_writer->_create_file();

0 commit comments

Comments
 (0)