@@ -349,31 +349,36 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
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char * subcircuit_stripped_name = get_stripped_name (subcircuit_name);
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/* check for coarse-grain configuration */
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if (configuration.coarsen ) {
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- new_node->type = yosys_subckt_strmap[subcircuit_name];
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+ if (yosys_subckt_strmap.find (subcircuit_name) != yosys_subckt_strmap.end ())
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+ new_node->type = yosys_subckt_strmap[subcircuit_name];
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- if (subcircuit_stripped_name && new_node->type == NO_OP)
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+ if (new_node->type == NO_OP && yosys_subckt_strmap. find (subcircuit_stripped_name) != yosys_subckt_strmap. end () )
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new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
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if (new_node->type == NO_OP) {
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char new_name[READ_BLIF_BUFFER];
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vtr::free (new_node->name );
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/* in case of weird names, need to add memories manually */
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- if (ports->count == 5 ) {
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+ int sc_spot = -1 ;
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+ char * yosys_subckt_str = NULL ;
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+ if ((yosys_subckt_str = retrieve_node_type_from_subckt_name (subcircuit_stripped_name)) != NULL ) {
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/* specify node type */
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- new_node->type = yosys_subckt_strmap[SINGLE_PORT_RAM_string ];
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+ new_node->type = yosys_subckt_strmap[yosys_subckt_str ];
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/* specify node name */
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- odin_sprintf (new_name, " \\ %s~%ld" , SINGLE_PORT_RAM_string, hard_block_number - 1 );
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- new_node->name = make_full_ref_name (new_name, NULL , NULL , NULL , -1 );
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- } else if (ports->count == 9 ) {
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+ odin_sprintf (new_name, " \\ %s~%ld" , yosys_subckt_str, hard_block_number - 1 );
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+ } else if ((sc_spot = sc_lookup_string (hard_block_names, subcircuit_stripped_name)) != -1 ) {
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/* specify node type */
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- new_node->type = yosys_subckt_strmap[DUAL_PORT_RAM_string] ;
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+ new_node->type = HARD_IP ;
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/* specify node name */
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- odin_sprintf (new_name, " \\ %s~%ld" , DUAL_PORT_RAM_string, hard_block_number - 1 );
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- new_node->name = make_full_ref_name (new_name, NULL , NULL , NULL , -1 );
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+ odin_sprintf (new_name, " \\ %s~%ld" , subcircuit_stripped_name, hard_block_number - 1 );
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} else {
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error_message (PARSE_BLIF, unknown_location,
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- " Unsupported sub-circuit type (%s) in BLIF file.\n " , subcircuit_name);
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+ " Unsupported subcircuit type (%s) in BLIF file.\n " , subcircuit_name);
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}
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+ new_node->name = make_full_ref_name (new_name, NULL , NULL , NULL , -1 );
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+
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+ // CLEAN UP
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+ vtr::free (yosys_subckt_str);
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}
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if (new_node->type == BRAM) {
@@ -410,7 +415,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
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if (!model)
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error_message (PARSE_BLIF, unknown_location,
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- " Failed to retrieve sub-circuit model (%s)\n " , subcircuit_name);
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+ " Failed to retrieve subcircuit model (%s)\n " , subcircuit_name);
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/* Add input and output ports to the new node. */
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else {
@@ -481,7 +486,7 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
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}
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// Create a fake ast node.
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- if (!configuration.coarsen ) {
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+ if (!configuration.coarsen || new_node-> type == HARD_IP ) {
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new_node->related_ast_node = create_node_w_type (HARD_BLOCK, my_location);
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new_node->related_ast_node ->children = (ast_node_t **)vtr::calloc (1 , sizeof (ast_node_t *));
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new_node->related_ast_node ->identifier_node = create_tree_node_id (vtr::strdup (subcircuit_name), my_location);
@@ -2147,8 +2152,11 @@ void BLIF::Reader::hard_block_sensitivities(const char* subckt_name, nnode_t* ne
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char * ptr;
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char * buffer = NULL ;
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attr_t * attributes = new_node->attributes ;
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+ operation_list op = (yosys_subckt_strmap.find (subckt_name) != yosys_subckt_strmap.end ())
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+ ? yosys_subckt_strmap[subckt_name]
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+ : NO_OP;
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- if (need_params (yosys_subckt_strmap[subckt_name] )) {
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+ if (need_params (op )) {
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while (getbline (buffer, READ_BLIF_BUFFER, file)) {
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my_location.line += 1 ;
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ptr = vtr::strtok (buffer, TOKENS, file, buffer);
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