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sdamghansdamghan
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[Yosys+Odin]: remove hardcodded DPRAM/SPRAM detection in BLIF Reader
Signed-off-by: Seyed Alireza Damghani <[email protected]>
1 parent 92c8b59 commit 5192448

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5 files changed

+53
-18
lines changed

5 files changed

+53
-18
lines changed

‎ODIN_II/SRC/BLIFReader.cpp

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -349,26 +349,23 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
349349
char* subcircuit_stripped_name = get_stripped_name(subcircuit_name);
350350
/* check for coarse-grain configuration */
351351
if (configuration.coarsen) {
352-
new_node->type = yosys_subckt_strmap[subcircuit_name];
352+
if (yosys_subckt_strmap.find(subcircuit_name) != yosys_subckt_strmap.end())
353+
new_node->type = yosys_subckt_strmap[subcircuit_name];
353354

354-
if (subcircuit_stripped_name && new_node->type == NO_OP)
355+
if (new_node->type == NO_OP && yosys_subckt_strmap.find(subcircuit_stripped_name) != yosys_subckt_strmap.end())
355356
new_node->type = yosys_subckt_strmap[subcircuit_stripped_name];
356357

357358
if (new_node->type == NO_OP) {
358359
char new_name[READ_BLIF_BUFFER];
359360
vtr::free(new_node->name);
360361
/* in case of weird names, need to add memories manually */
361362
int sc_spot = -1;
362-
if (std::string(subcircuit_stripped_name).find(SINGLE_PORT_RAM_string, 0) != std::string::npos) {
363-
/* specify node type */
364-
new_node->type = yosys_subckt_strmap[SINGLE_PORT_RAM_string];
365-
/* specify node name */
366-
odin_sprintf(new_name, "\\%s~%ld", SINGLE_PORT_RAM_string, hard_block_number - 1);
367-
} else if (std::string(subcircuit_stripped_name).find(DUAL_PORT_RAM_string, 0) != std::string::npos) {
363+
char* yosys_subckt_str = NULL;
364+
if ((yosys_subckt_str = retrieve_node_type_from_subckt_name(subcircuit_stripped_name)) != NULL) {
368365
/* specify node type */
369-
new_node->type = yosys_subckt_strmap[DUAL_PORT_RAM_string];
366+
new_node->type = yosys_subckt_strmap[yosys_subckt_str];
370367
/* specify node name */
371-
odin_sprintf(new_name, "\\%s~%ld", DUAL_PORT_RAM_string, hard_block_number - 1);
368+
odin_sprintf(new_name, "\\%s~%ld", yosys_subckt_str, hard_block_number - 1);
372369
} else if ((sc_spot = sc_lookup_string(hard_block_names, subcircuit_stripped_name)) != -1) {
373370
/* specify node type */
374371
new_node->type = HARD_IP;
@@ -379,6 +376,9 @@ void BLIF::Reader::create_hard_block_nodes(hard_block_models* models) {
379376
"Unsupported subcircuit type (%s) in BLIF file.\n", subcircuit_name);
380377
}
381378
new_node->name = make_full_ref_name(new_name, NULL, NULL, NULL, -1);
379+
380+
// CLEAN UP
381+
vtr::free(yosys_subckt_str);
382382
}
383383

384384
if (new_node->type == BRAM) {
@@ -2152,8 +2152,11 @@ void BLIF::Reader::hard_block_sensitivities(const char* subckt_name, nnode_t* ne
21522152
char* ptr;
21532153
char* buffer = NULL;
21542154
attr_t* attributes = new_node->attributes;
2155+
operation_list op = (yosys_subckt_strmap.find(subckt_name) != yosys_subckt_strmap.end())
2156+
? yosys_subckt_strmap[subckt_name]
2157+
: NO_OP;
21552158

2156-
if (need_params(yosys_subckt_strmap[subckt_name])) {
2159+
if (need_params(op)) {
21572160
while (getbline(buffer, READ_BLIF_BUFFER, file)) {
21582161
my_location.line += 1;
21592162
ptr = vtr::strtok(buffer, TOKENS, file, buffer);

‎ODIN_II/SRC/include/odin_util.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ char* get_pin_name(char* name);
5959
char* get_port_name(char* name);
6060
char* get_hard_block_node_name(char* name);
6161
char* get_stripped_name(const char* subcircuit_name);
62+
char* retrieve_node_type_from_subckt_name(const char* subcircuit_name);
6263
int get_pin_number(char* name);
6364
short get_bit(char in);
6465
short get_bit(short in);

‎ODIN_II/SRC/odin_util.cpp

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -669,9 +669,40 @@ char* get_stripped_name(const char* subcircuit_name) {
669669
subcircuit_stripped_name[5] = '\0';
670670
}
671671

672+
if (subcircuit_stripped_name == NULL)
673+
return (vtr::strdup(subcircuit_name));
674+
672675
return (subcircuit_stripped_name);
673676
}
674677

678+
/**
679+
*---------------------------------------------------------------------------------------------
680+
* (function: retrieve_node_type_from_subckt_name)
681+
*
682+
* @brief to retrieve the actual node type from the subcircuit name
683+
* in cases where yosys generates a weird name, which includes port
684+
* widths and additional information in a subcircuit name
685+
*
686+
* @param stripped_name subcircuit irregular name
687+
*
688+
* @return the actual subcircuit name if it was successfully
689+
* retrieved, otherwise NULL pointer
690+
* -------------------------------------------------------------------------------------------
691+
*/
692+
char* retrieve_node_type_from_subckt_name(const char* subcircuit_name) {
693+
/* validation */
694+
oassert(subcircuit_name);
695+
696+
/* looking for Yosys style generated RTLIL module name */
697+
if (true) {
698+
for (auto pair : yosys_subckt_strmap)
699+
if (std::string(subcircuit_name).find(pair.first, 0) != std::string::npos)
700+
return vtr::strdup(pair.first.c_str());
701+
}
702+
703+
return (NULL);
704+
}
705+
675706
/*
676707
* Gets the pin number (the number after the ~)
677708
* from the given name.

‎ODIN_II/regression_test/benchmark/task/yosys+odin/koios/synthesis_result.json

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4688,11 +4688,11 @@
46884688
"[NETLIST] requesting a shift left that will overflow the maximum size of 255 [63]"
46894689
],
46904690
"max_rss(MiB)": 2372.7,
4691-
"exec_time(ms)": 18585.2,
4691+
"exec_time(ms)": 4802463.9,
46924692
"elaboration_time(ms)": 12798.1,
46934693
"optimization_time(ms)": 37.9,
4694-
"techmap_time(ms)": 3862,
4695-
"synthesis_time(ms)": 16698,
4694+
"techmap_time(ms)": 4773374.4,
4695+
"synthesis_time(ms)": 4797356.4,
46964696
"Latch Drivers": 1,
46974697
"Pi": 790,
46984698
"Po": 2283,
@@ -5687,7 +5687,7 @@
56875687
"exec_time(ms)": 8816.9,
56885688
"elaboration_time(ms)": 7419.6,
56895689
"optimization_time(ms)": 11.9,
5690-
"techmap_time(ms)": 956.9,
5690+
"techmap_time(ms)": 275436.4,
56915691
"synthesis_time(ms)": 8388.5,
56925692
"Latch Drivers": 1,
56935693
"Pi": 1,

‎ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -137,11 +137,11 @@
137137
"architecture": "k6_frac_N10_frac_chain_mem32K_40nm.xml",
138138
"verilog": "LargeRam.v",
139139
"max_rss(MiB)": 6326.8,
140-
"exec_time(ms)": 24197.5,
140+
"exec_time(ms)": 9226014.3,
141141
"elaboration_time(ms)": 35,
142-
"optimization_time(ms)": 10133,
142+
"optimization_time(ms)": 9177403.5,
143143
"techmap_time(ms)": 6358.1,
144-
"synthesis_time(ms)": 16526.1,
144+
"synthesis_time(ms)": 9203921.3,
145145
"Pi": 37,
146146
"Po": 2,
147147
"logic element": 2883573,

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