vpr: netlist writer: don't concat multi bit ports

Instead of concating multi bit ports set each bit separately

Signed-off-by: Paweł Czarnecki <[email protected]>

Author: lpawelcz

vpr/src/base/netlist_writer.cpp

@@ -2433,12 +2433,11 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
         }
     };
 
-    //Port name
-    os << indent(depth) << "." << port_name << "(";
-
     //Pins
     if (nets.size() == 1) {
         //Single-bit port
+	//Port name
+	os << indent(depth) << "." << port_name << "(";
         if (nets[0].empty()) {
             //Disconnected
             if (type == PortType::INPUT || type == PortType::CLOCK) {
@@ -2451,6 +2450,7 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
             //Connected
             os << escape_verilog_identifier(nets[0]);
         }
+	os << ")";
     } else {
         // Check if all pins are unconnected
         bool all_unconnected = true;
@@ -2467,10 +2467,10 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
             // Empty connection
         } else {
             // Individual bits
-            os << "{"
-               << "\n";
             for (int ipin = (int)nets.size() - 1; ipin >= 0; --ipin) { //Reverse order to match endianess
-                os << indent(depth + 1);
+                //Port name
+                std::string name = port_name + "[" + std::to_string(ipin) + "]";
+                os << indent(depth) << "." << escape_verilog_identifier(name) << "(";
                 if (nets[ipin].empty()) {
                     //Disconnected
                     if (type == PortType::INPUT || type == PortType::CLOCK) {
@@ -2486,15 +2486,14 @@ void print_verilog_port(std::ostream& os, size_t& unconn_count, const std::strin
                     //Connected
                     os << escape_verilog_identifier(nets[ipin]);
                 }
+            	os << ")";
                 if (ipin != 0) {
                     os << ",";
                 }
                 os << "\n";
             }
-            os << indent(depth) + " }";
         }
     }
-    os << ")";
 }
 
 ///@brief Escapes the given identifier to be safe for verilog