Initial FPGA Interchange rr_graph builder

Signed-off-by: Maciej Dudek <[email protected]>

Author: mtdudek

vpr/src/base/SetupVPR.cpp

@@ -422,6 +422,7 @@ static void SetupRouterOpts(const t_options& Options, t_router_opts* RouterOpts)
 
     RouterOpts->max_logged_overused_rr_nodes = Options.max_logged_overused_rr_nodes;
     RouterOpts->generate_rr_node_overuse_report = Options.generate_rr_node_overuse_report;
+    RouterOpts->FPGAInterchange = Options.FPGAInterchangeDevice;
 }
 
 static void SetupAnnealSched(const t_options& Options,

vpr/src/route/rr_graph.cpp

@@ -31,6 +31,7 @@
 #include "build_switchblocks.h"
 #include "rr_graph_writer.h"
 #include "rr_graph_reader.h"
+#include "rr_graph_fpga_interchange.h"
 #include "router_lookahead_map.h"
 #include "rr_graph_clock.h"
 #include "edge_groups.h"
@@ -315,7 +316,8 @@ void create_rr_graph(const t_graph_type graph_type,
                      int* Warnings) {
     const auto& device_ctx = g_vpr_ctx.device();
     auto& mutable_device_ctx = g_vpr_ctx.mutable_device();
-    if (!det_routing_arch->read_rr_graph_filename.empty()) {
+
+    if (!det_routing_arch->read_rr_graph_filename.empty() || router_opts.FPGAInterchange) {
         if (device_ctx.read_rr_graph_filename != det_routing_arch->read_rr_graph_filename) {
             free_rr_graph();
 
@@ -332,6 +334,25 @@ void create_rr_graph(const t_graph_type graph_type,
                                                                   router_opts.reorder_rr_graph_nodes_threshold,
                                                                   router_opts.reorder_rr_graph_nodes_seed);
             }
+        } else if (!device_ctx.read_rr_graph_filename.size() && router_opts.FPGAInterchange) {
+            free_rr_graph();
+
+            VTR_LOG("Custom RR_graph generator\n");
+            build_rr_graph_fpga_interchange(graph_type,
+                                            grid,
+                                            segment_inf,
+                                            router_opts.base_cost_type,
+                                            &det_routing_arch->wire_to_rr_ipin_switch,
+                                            det_routing_arch->read_rr_graph_filename.c_str(),
+                                            router_opts.read_rr_edge_metadata,
+                                            router_opts.do_check_rr_graph);
+
+            exit(0);
+            if (router_opts.reorder_rr_graph_nodes_algorithm != DONT_REORDER) {
+                mutable_device_ctx.rr_graph_builder.reorder_nodes(router_opts.reorder_rr_graph_nodes_algorithm,
+                                                                  router_opts.reorder_rr_graph_nodes_threshold,
+                                                                  router_opts.reorder_rr_graph_nodes_seed);
+            }
         }
     } else {
         if (channel_widths_unchanged(device_ctx.chan_width, nodes_per_chan) && !device_ctx.rr_graph.empty()) {

vpr/src/route/rr_graph_fpga_interchange.cpp

@@ -0,0 +1,21 @@
+#include "rr_graph_fpga_interchange.h"
+
+#include "arch_util.h"
+#include "vtr_time.h"
+#include "globals.h"
+
+void build_rr_graph_fpga_interchange(const t_graph_type graph_type,
+                                     const DeviceGrid& grid,
+                                     const std::vector<t_segment_inf>& segment_inf,
+                                     const enum e_base_cost_type base_cost_type,
+                                     int* wire_to_rr_ipin_switch,
+                                     const char* read_rr_graph_name,
+                                     bool read_edge_metadata,
+                                     bool do_check_rr_graph) {
+    vtr::ScopedStartFinishTimer timer("Building RR Graph from device database");
+
+    auto& device_ctx = g_vpr_ctx.mutable_device();
+    device_ctx.rr_segments = segment_inf;
+
+    VTR_LOG("%s\n", get_arch_file_name());
+};

vpr/src/route/rr_graph_fpga_interchange.h

@@ -0,0 +1,18 @@
+/* Defines the function used to load an rr graph written in xml format into vpr*/
+
+#ifndef RR_GRAPH_FPGA_INTERCHANGE_H
+#define RR_GRAPH_FPGA_INTERCHANGE_H
+
+#include "rr_graph.h"
+#include "device_grid.h"
+
+void build_rr_graph_fpga_interchange(const t_graph_type graph_type,
+                                     const DeviceGrid& grid,
+                                     const std::vector<t_segment_inf>& segment_inf,
+                                     const enum e_base_cost_type base_cost_type,
+                                     int* wire_to_rr_ipin_switch,
+                                     const char* read_rr_graph_name,
+                                     bool read_edge_metadata,
+                                     bool do_check_rr_graph);
+
+#endif /* RR_GRAPH_FPGA_INTERCHANGE_H */