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// File local type declarations
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//
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- typedef std::pair<double , std::string> pair_d ;
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+ typedef std::pair<double , std::string> sequential_port_delay_pair ;
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/* enum class PortType {
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* IN,
@@ -555,9 +555,9 @@ class BlackBoxInst : public Instance {
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std::map<std::string, std::vector<std::string>> input_port_conns, // /<Port connections: Dictionary of <port,nets>
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std::map<std::string, std::vector<std::string>> output_port_conns, // /<Port connections: Dictionary of <port,nets>
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std::vector<Arc> timing_arcs, // /<Combinational timing arcs
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- std::map<std::string, pair_d > ports_tsu, // /<Port setup checks
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- std::map<std::string, pair_d > ports_thld, // /<Port hold checks
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- std::map<std::string, pair_d > ports_tcq) // /<Port clock-to-q delays
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+ std::map<std::string, sequential_port_delay_pair > ports_tsu, // /<Port setup checks
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+ std::map<std::string, sequential_port_delay_pair > ports_thld, // /<Port hold checks
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+ std::map<std::string, sequential_port_delay_pair > ports_tcq) // /<Port clock-to-q delays
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: type_name_(type_name)
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, inst_name_(inst_name)
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, params_(params)
@@ -567,7 +567,7 @@ class BlackBoxInst : public Instance {
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, timing_arcs_(timing_arcs)
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, ports_tsu_(ports_tsu)
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, ports_thld_(ports_thld)
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- , ports_tcq_(ports_tcq){}
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+ , ports_tcq_(ports_tcq) {}
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void print_blif (std::ostream& os, size_t & unconn_count, int depth = 0 ) override {
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os << indent (depth) << " .subckt " << type_name_ << " \\ "
@@ -652,80 +652,77 @@ class BlackBoxInst : public Instance {
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}
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void print_sdf (std::ostream& os, int depth = 0 ) override {
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-
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-
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if (!timing_arcs_.empty () || !ports_tcq_.empty () || !ports_tsu_.empty () || !ports_thld_.empty ()) {
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- os << indent (depth) << " (CELL\n " ;
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- os << indent (depth + 1 ) << " (CELLTYPE \" " << type_name_ << " \" )\n " ;
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- os << indent (depth + 1 ) << " (INSTANCE " << escape_sdf_identifier (inst_name_) << " )\n " ;
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- os << indent (depth + 1 ) << " (DELAY\n " ;
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-
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-
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- if (!timing_arcs_.empty () || !ports_tcq_.empty ()) {
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- os << indent (depth + 2 ) << " (ABSOLUTE\n " ;
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-
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- // Combinational paths
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- for (const auto & arc : timing_arcs_) {
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- double delay_ps = get_delay_ps (arc.delay ());
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-
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- std::stringstream delay_triple;
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- delay_triple << " (" << delay_ps << " :" << delay_ps << " :" << delay_ps << " )" ;
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-
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- // Note that we explicitly do not escape the last array indexing so an SDF
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- // reader will treat the ports as multi-bit
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- //
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- // We also only put the last index in if the port has multiple bits
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- os << indent (depth + 3 ) << " (IOPATH " ;
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- os << escape_sdf_identifier (arc.source_name ());
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- if (find_port_size (arc.source_name ()) > 1 ) {
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- os << " [" << arc.source_ipin () << " ]" ;
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- }
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- os << " " ;
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- os << escape_sdf_identifier (arc.sink_name ());
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- if (find_port_size (arc.sink_name ()) > 1 ) {
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- os << " [" << arc.sink_ipin () << " ]" ;
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- }
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- os << " " ;
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- os << delay_triple.str ();
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- os << " )\n " ;
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- }
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-
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- // Clock-to-Q delays
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- for (auto kv : ports_tcq_) {
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- double clock_to_q_ps = get_delay_ps (kv.second .first );
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-
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- std::stringstream delay_triple;
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- delay_triple << " (" << clock_to_q_ps << " :" << clock_to_q_ps << " :" << clock_to_q_ps << " )" ;
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-
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- os << indent (depth + 3 ) << " (IOPATH (posedge " << escape_sdf_identifier (kv.second .second ) << " ) " << escape_sdf_identifier (kv.first ) << " " << delay_triple.str () << " " << delay_triple.str () << " )\n " ;
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- }
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- os << indent (depth + 2 ) << " )\n " ; // ABSOLUTE
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- }
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- os << indent (depth + 1 ) << " )\n " ; // DELAY
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-
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- if (!ports_tsu_.empty () || !ports_thld_.empty ()) {
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- // Setup checks
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- os << indent (depth + 1 ) << " (TIMINGCHECK\n " ;
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- for (auto kv : ports_tsu_) {
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- double setup_ps = get_delay_ps (kv.second .first );
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-
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- std::stringstream delay_triple;
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- delay_triple << " (" << setup_ps << " :" << setup_ps << " :" << setup_ps << " )" ;
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-
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- os << indent (depth + 2 ) << " (SETUP " << escape_sdf_identifier (kv.first ) << " (posedge " << escape_sdf_identifier (kv.second .second ) << " ) " << delay_triple.str () << " )\n " ;
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- }
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- for (auto kv : ports_thld_) {
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- double hold_ps = get_delay_ps (kv.second .first );
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-
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- std::stringstream delay_triple;
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- delay_triple << " (" << hold_ps << " :" << hold_ps << " :" << hold_ps << " )" ;
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-
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- os << indent (depth + 2 ) << " (HOLD " << escape_sdf_identifier (kv.first ) << " (posedge " << escape_sdf_identifier (kv.second .second ) << " ) " << delay_triple.str () << " )\n " ;
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- }
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- os << indent (depth + 1 ) << " )\n " ; // TIMINGCHECK
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- }
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- os << indent (depth) << " )\n " ; // CELL
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- }
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+ os << indent (depth) << " (CELL\n " ;
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+ os << indent (depth + 1 ) << " (CELLTYPE \" " << type_name_ << " \" )\n " ;
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+ os << indent (depth + 1 ) << " (INSTANCE " << escape_sdf_identifier (inst_name_) << " )\n " ;
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+ os << indent (depth + 1 ) << " (DELAY\n " ;
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+
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+ if (!timing_arcs_.empty () || !ports_tcq_.empty ()) {
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+ os << indent (depth + 2 ) << " (ABSOLUTE\n " ;
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+
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+ // Combinational paths
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+ for (const auto & arc : timing_arcs_) {
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+ double delay_ps = get_delay_ps (arc.delay ());
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+
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+ std::stringstream delay_triple;
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+ delay_triple << " (" << delay_ps << " :" << delay_ps << " :" << delay_ps << " )" ;
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+
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+ // Note that we explicitly do not escape the last array indexing so an SDF
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+ // reader will treat the ports as multi-bit
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+ //
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+ // We also only put the last index in if the port has multiple bits
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+ os << indent (depth + 3 ) << " (IOPATH " ;
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+ os << escape_sdf_identifier (arc.source_name ());
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+ if (find_port_size (arc.source_name ()) > 1 ) {
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+ os << " [" << arc.source_ipin () << " ]" ;
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+ }
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+ os << " " ;
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+ os << escape_sdf_identifier (arc.sink_name ());
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+ if (find_port_size (arc.sink_name ()) > 1 ) {
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+ os << " [" << arc.sink_ipin () << " ]" ;
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+ }
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+ os << " " ;
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+ os << delay_triple.str ();
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+ os << " )\n " ;
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+ }
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+
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+ // Clock-to-Q delays
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+ for (auto kv : ports_tcq_) {
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+ double clock_to_q_ps = get_delay_ps (kv.second .first );
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+
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+ std::stringstream delay_triple;
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+ delay_triple << " (" << clock_to_q_ps << " :" << clock_to_q_ps << " :" << clock_to_q_ps << " )" ;
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+
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+ os << indent (depth + 3 ) << " (IOPATH (posedge " << escape_sdf_identifier (kv.second .second ) << " ) " << escape_sdf_identifier (kv.first ) << " " << delay_triple.str () << " " << delay_triple.str () << " )\n " ;
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+ }
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+ os << indent (depth + 2 ) << " )\n " ; // ABSOLUTE
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+ }
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+ os << indent (depth + 1 ) << " )\n " ; // DELAY
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+
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+ if (!ports_tsu_.empty () || !ports_thld_.empty ()) {
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+ // Setup checks
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+ os << indent (depth + 1 ) << " (TIMINGCHECK\n " ;
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+ for (auto kv : ports_tsu_) {
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+ double setup_ps = get_delay_ps (kv.second .first );
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+
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+ std::stringstream delay_triple;
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+ delay_triple << " (" << setup_ps << " :" << setup_ps << " :" << setup_ps << " )" ;
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+
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+ os << indent (depth + 2 ) << " (SETUP " << escape_sdf_identifier (kv.first ) << " (posedge " << escape_sdf_identifier (kv.second .second ) << " ) " << delay_triple.str () << " )\n " ;
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+ }
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+ for (auto kv : ports_thld_) {
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+ double hold_ps = get_delay_ps (kv.second .first );
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+
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+ std::stringstream delay_triple;
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+ delay_triple << " (" << hold_ps << " :" << hold_ps << " :" << hold_ps << " )" ;
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+
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+ os << indent (depth + 2 ) << " (HOLD " << escape_sdf_identifier (kv.first ) << " (posedge " << escape_sdf_identifier (kv.second .second ) << " ) " << delay_triple.str () << " )\n " ;
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+ }
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+ os << indent (depth + 1 ) << " )\n " ; // TIMINGCHECK
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+ }
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+ os << indent (depth) << " )\n " ; // CELL
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+ }
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}
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size_t find_port_size (std::string port_name) {
@@ -752,9 +749,9 @@ class BlackBoxInst : public Instance {
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std::map<std::string, std::vector<std::string>> input_port_conns_;
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std::map<std::string, std::vector<std::string>> output_port_conns_;
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std::vector<Arc> timing_arcs_;
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- std::map<std::string, pair_d > ports_tsu_;
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- std::map<std::string, pair_d > ports_thld_;
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- std::map<std::string, pair_d > ports_tcq_;
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+ std::map<std::string, sequential_port_delay_pair > ports_tsu_;
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+ std::map<std::string, sequential_port_delay_pair > ports_thld_;
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+ std::map<std::string, sequential_port_delay_pair > ports_tcq_;
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};
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/* *
@@ -902,7 +899,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
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verilog_os_ << indent (depth + 1 ) << " wire " << escape_verilog_identifier (wire_tnode_pair.first ) << " ;\n " ;
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}
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}
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-
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+
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verilog_os_ << indent (depth + 1 ) << " wire DummyOut;\n " ;
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// connections between primary I/Os and their internal wires
@@ -1288,9 +1285,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
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std::map<std::string, std::vector<std::string>> input_port_conns;
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std::map<std::string, std::vector<std::string>> output_port_conns;
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std::vector<Arc> timing_arcs;
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- std::map<std::string, pair_d > ports_tsu;
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- std::map<std::string, pair_d > ports_thld;
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- std::map<std::string, pair_d > ports_tcq;
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+ std::map<std::string, sequential_port_delay_pair > ports_tsu;
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+ std::map<std::string, sequential_port_delay_pair > ports_thld;
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+ std::map<std::string, sequential_port_delay_pair > ports_tcq;
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params[" ADDR_WIDTH" ] = " 0" ;
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params[" DATA_WIDTH" ] = " 0" ;
@@ -1382,7 +1379,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
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" Unrecognized input port class '%s' for primitive '%s' (%s)\n " , port_class.c_str (), atom->name , pb_type->name );
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}
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output_port_conns[port_name].push_back (net);
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- ports_tcq[port_name] = std::make_pair (pin->tco_max ,pin->associated_clock_pin ->port ->name ); // pin->tco_max ;
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+ ports_tcq[port_name] = std::make_pair (pin->tco_max , pin->associated_clock_pin ->port ->name );
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}
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}
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@@ -1431,9 +1428,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
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std::map<std::string, std::vector<std::string>> input_port_conns;
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std::map<std::string, std::vector<std::string>> output_port_conns;
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std::vector<Arc> timing_arcs;
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- std::map<std::string, pair_d > ports_tsu;
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- std::map<std::string, pair_d > ports_thld;
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- std::map<std::string, pair_d > ports_tcq;
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+ std::map<std::string, sequential_port_delay_pair > ports_tsu;
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+ std::map<std::string, sequential_port_delay_pair > ports_thld;
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+ std::map<std::string, sequential_port_delay_pair > ports_tcq;
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params[" WIDTH" ] = " 0" ;
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@@ -1527,9 +1524,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
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std::map<std::string, std::vector<std::string>> input_port_conns;
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std::map<std::string, std::vector<std::string>> output_port_conns;
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std::vector<Arc> timing_arcs;
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- std::map<std::string, pair_d > ports_tsu;
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- std::map<std::string, pair_d > ports_thld;
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- std::map<std::string, pair_d > ports_tcq;
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+ std::map<std::string, sequential_port_delay_pair > ports_tsu;
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+ std::map<std::string, sequential_port_delay_pair > ports_thld;
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+ std::map<std::string, sequential_port_delay_pair > ports_tcq;
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params[" WIDTH" ] = " 0" ;
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@@ -1625,9 +1622,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
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std::map<std::string, std::vector<std::string>> input_port_conns;
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std::map<std::string, std::vector<std::string>> output_port_conns;
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std::vector<Arc> timing_arcs;
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- std::map<std::string, pair_d > ports_tsu;
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- std::map<std::string, pair_d > ports_thld;
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- std::map<std::string, pair_d > ports_tcq;
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+ std::map<std::string, sequential_port_delay_pair > ports_tsu;
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+ std::map<std::string, sequential_port_delay_pair > ports_thld;
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+ std::map<std::string, sequential_port_delay_pair > ports_tcq;
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// Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay
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std::map<tatum::NodeId, std::vector<std::tuple<std::string, int , double >>> tnode_delay_matrix;
@@ -1663,16 +1660,15 @@ class NetlistWriterVisitor : public NetlistVisitor {
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}
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}
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+ input_port_conns[port->name ].push_back (net);
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+ if (pin->type == PB_PIN_SEQUENTIAL) {
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+ if (!std::isnan (pin->tsu )) ports_tsu[port->name ] = std::make_pair (pin->tsu , pin->associated_clock_pin ->port ->name );
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+ if (!std::isnan (pin->thld )) ports_thld[port->name ] = std::make_pair (pin->thld , pin->associated_clock_pin ->port ->name );
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+ }
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+ }
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+ }
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- input_port_conns[port->name ].push_back (net);
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- if (pin->type == PB_PIN_SEQUENTIAL) {
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- if (!std::isnan (pin->tsu )) ports_tsu[port->name ] = std::make_pair (pin->tsu , pin->associated_clock_pin ->port ->name );
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- if (!std::isnan (pin->thld )) ports_thld[port->name ] = std::make_pair (pin->thld , pin->associated_clock_pin ->port ->name );
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- }
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- }
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- }
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-
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- // Process the output ports
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+ // Process the output ports
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for (int iport = 0 ; iport < pb_graph_node->num_output_ports ; ++iport) {
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for (int ipin = 0 ; ipin < pb_graph_node->num_output_pins [iport]; ++ipin) {
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const t_pb_graph_pin* pin = &pb_graph_node->output_pins [iport][ipin];
@@ -1682,7 +1678,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
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std::string net;
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if (!top_pb_route.count (cluster_pin_idx)) {
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- // Disconnected
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+ // Disconnected
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net = " " ;
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} else {
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// Connected
@@ -1700,9 +1696,8 @@ class NetlistWriterVisitor : public NetlistVisitor {
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}
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}
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-
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output_port_conns[port->name ].push_back (net);
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- if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan (pin->tco_max )) ports_tcq[port->name ] = std::make_pair (pin->tco_max ,pin->associated_clock_pin ->port ->name );
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+ if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan (pin->tco_max )) ports_tcq[port->name ] = std::make_pair (pin->tco_max , pin->associated_clock_pin ->port ->name );
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}
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}
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