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Terachand Pagaraniacomodi
Terachand Pagarani
authored and
acomodi
committed
formatting changes based on review feedback
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‎vpr/src/base/netlist_writer.cpp

Lines changed: 102 additions & 107 deletions
Original file line numberDiff line numberDiff line change
@@ -92,7 +92,7 @@
9292
//File local type declarations
9393
//
9494

95-
typedef std::pair<double, std::string> pair_d;
95+
typedef std::pair<double, std::string> sequential_port_delay_pair;
9696

9797
/*enum class PortType {
9898
* IN,
@@ -555,9 +555,9 @@ class BlackBoxInst : public Instance {
555555
std::map<std::string, std::vector<std::string>> input_port_conns, ///<Port connections: Dictionary of <port,nets>
556556
std::map<std::string, std::vector<std::string>> output_port_conns, ///<Port connections: Dictionary of <port,nets>
557557
std::vector<Arc> timing_arcs, ///<Combinational timing arcs
558-
std::map<std::string, pair_d> ports_tsu, ///<Port setup checks
559-
std::map<std::string, pair_d> ports_thld, ///<Port hold checks
560-
std::map<std::string, pair_d> ports_tcq) ///<Port clock-to-q delays
558+
std::map<std::string, sequential_port_delay_pair> ports_tsu, ///<Port setup checks
559+
std::map<std::string, sequential_port_delay_pair> ports_thld, ///<Port hold checks
560+
std::map<std::string, sequential_port_delay_pair> ports_tcq) ///<Port clock-to-q delays
561561
: type_name_(type_name)
562562
, inst_name_(inst_name)
563563
, params_(params)
@@ -567,7 +567,7 @@ class BlackBoxInst : public Instance {
567567
, timing_arcs_(timing_arcs)
568568
, ports_tsu_(ports_tsu)
569569
, ports_thld_(ports_thld)
570-
, ports_tcq_(ports_tcq){}
570+
, ports_tcq_(ports_tcq) {}
571571

572572
void print_blif(std::ostream& os, size_t& unconn_count, int depth = 0) override {
573573
os << indent(depth) << ".subckt " << type_name_ << " \\"
@@ -652,80 +652,77 @@ class BlackBoxInst : public Instance {
652652
}
653653

654654
void print_sdf(std::ostream& os, int depth = 0) override {
655-
656-
657655
if (!timing_arcs_.empty() || !ports_tcq_.empty() || !ports_tsu_.empty() || !ports_thld_.empty()) {
658-
os << indent(depth) << "(CELL\n";
659-
os << indent(depth + 1) << "(CELLTYPE \"" << type_name_ << "\")\n";
660-
os << indent(depth + 1) << "(INSTANCE " << escape_sdf_identifier(inst_name_) << ")\n";
661-
os << indent(depth + 1) << "(DELAY\n";
662-
663-
664-
if (!timing_arcs_.empty() || !ports_tcq_.empty()) {
665-
os << indent(depth + 2) << "(ABSOLUTE\n";
666-
667-
//Combinational paths
668-
for (const auto& arc : timing_arcs_) {
669-
double delay_ps = get_delay_ps(arc.delay());
670-
671-
std::stringstream delay_triple;
672-
delay_triple << "(" << delay_ps << ":" << delay_ps << ":" << delay_ps << ")";
673-
674-
//Note that we explicitly do not escape the last array indexing so an SDF
675-
//reader will treat the ports as multi-bit
676-
//
677-
//We also only put the last index in if the port has multiple bits
678-
os << indent(depth + 3) << "(IOPATH ";
679-
os << escape_sdf_identifier(arc.source_name());
680-
if (find_port_size(arc.source_name()) > 1) {
681-
os << "[" << arc.source_ipin() << "]";
682-
}
683-
os << " ";
684-
os << escape_sdf_identifier(arc.sink_name());
685-
if (find_port_size(arc.sink_name()) > 1) {
686-
os << "[" << arc.sink_ipin() << "]";
687-
}
688-
os << " ";
689-
os << delay_triple.str();
690-
os << ")\n";
691-
}
692-
693-
//Clock-to-Q delays
694-
for (auto kv : ports_tcq_) {
695-
double clock_to_q_ps = get_delay_ps(kv.second.first);
696-
697-
std::stringstream delay_triple;
698-
delay_triple << "(" << clock_to_q_ps << ":" << clock_to_q_ps << ":" << clock_to_q_ps << ")";
699-
700-
os << indent(depth + 3) << "(IOPATH (posedge " << escape_sdf_identifier(kv.second.second) << ") " << escape_sdf_identifier(kv.first) << " " << delay_triple.str() << " " << delay_triple.str() << ")\n";
701-
}
702-
os << indent(depth + 2) << ")\n"; //ABSOLUTE
703-
}
704-
os << indent(depth + 1) << ")\n"; //DELAY
705-
706-
if (!ports_tsu_.empty() || !ports_thld_.empty()) {
707-
//Setup checks
708-
os << indent(depth + 1) << "(TIMINGCHECK\n";
709-
for (auto kv : ports_tsu_) {
710-
double setup_ps = get_delay_ps(kv.second.first);
711-
712-
std::stringstream delay_triple;
713-
delay_triple << "(" << setup_ps << ":" << setup_ps << ":" << setup_ps << ")";
714-
715-
os << indent(depth + 2) << "(SETUP " << escape_sdf_identifier(kv.first) << " (posedge " << escape_sdf_identifier(kv.second.second) << ") " << delay_triple.str() << ")\n";
716-
}
717-
for (auto kv : ports_thld_) {
718-
double hold_ps = get_delay_ps(kv.second.first);
719-
720-
std::stringstream delay_triple;
721-
delay_triple << "(" << hold_ps << ":" << hold_ps << ":" << hold_ps << ")";
722-
723-
os << indent(depth + 2) << "(HOLD " << escape_sdf_identifier(kv.first) << " (posedge " << escape_sdf_identifier(kv.second.second) << ") " << delay_triple.str() << ")\n";
724-
}
725-
os << indent(depth + 1) << ")\n"; //TIMINGCHECK
726-
}
727-
os << indent(depth) << ")\n"; //CELL
728-
}
656+
os << indent(depth) << "(CELL\n";
657+
os << indent(depth + 1) << "(CELLTYPE \"" << type_name_ << "\")\n";
658+
os << indent(depth + 1) << "(INSTANCE " << escape_sdf_identifier(inst_name_) << ")\n";
659+
os << indent(depth + 1) << "(DELAY\n";
660+
661+
if (!timing_arcs_.empty() || !ports_tcq_.empty()) {
662+
os << indent(depth + 2) << "(ABSOLUTE\n";
663+
664+
//Combinational paths
665+
for (const auto& arc : timing_arcs_) {
666+
double delay_ps = get_delay_ps(arc.delay());
667+
668+
std::stringstream delay_triple;
669+
delay_triple << "(" << delay_ps << ":" << delay_ps << ":" << delay_ps << ")";
670+
671+
//Note that we explicitly do not escape the last array indexing so an SDF
672+
//reader will treat the ports as multi-bit
673+
//
674+
//We also only put the last index in if the port has multiple bits
675+
os << indent(depth + 3) << "(IOPATH ";
676+
os << escape_sdf_identifier(arc.source_name());
677+
if (find_port_size(arc.source_name()) > 1) {
678+
os << "[" << arc.source_ipin() << "]";
679+
}
680+
os << " ";
681+
os << escape_sdf_identifier(arc.sink_name());
682+
if (find_port_size(arc.sink_name()) > 1) {
683+
os << "[" << arc.sink_ipin() << "]";
684+
}
685+
os << " ";
686+
os << delay_triple.str();
687+
os << ")\n";
688+
}
689+
690+
//Clock-to-Q delays
691+
for (auto kv : ports_tcq_) {
692+
double clock_to_q_ps = get_delay_ps(kv.second.first);
693+
694+
std::stringstream delay_triple;
695+
delay_triple << "(" << clock_to_q_ps << ":" << clock_to_q_ps << ":" << clock_to_q_ps << ")";
696+
697+
os << indent(depth + 3) << "(IOPATH (posedge " << escape_sdf_identifier(kv.second.second) << ") " << escape_sdf_identifier(kv.first) << " " << delay_triple.str() << " " << delay_triple.str() << ")\n";
698+
}
699+
os << indent(depth + 2) << ")\n"; //ABSOLUTE
700+
}
701+
os << indent(depth + 1) << ")\n"; //DELAY
702+
703+
if (!ports_tsu_.empty() || !ports_thld_.empty()) {
704+
//Setup checks
705+
os << indent(depth + 1) << "(TIMINGCHECK\n";
706+
for (auto kv : ports_tsu_) {
707+
double setup_ps = get_delay_ps(kv.second.first);
708+
709+
std::stringstream delay_triple;
710+
delay_triple << "(" << setup_ps << ":" << setup_ps << ":" << setup_ps << ")";
711+
712+
os << indent(depth + 2) << "(SETUP " << escape_sdf_identifier(kv.first) << " (posedge " << escape_sdf_identifier(kv.second.second) << ") " << delay_triple.str() << ")\n";
713+
}
714+
for (auto kv : ports_thld_) {
715+
double hold_ps = get_delay_ps(kv.second.first);
716+
717+
std::stringstream delay_triple;
718+
delay_triple << "(" << hold_ps << ":" << hold_ps << ":" << hold_ps << ")";
719+
720+
os << indent(depth + 2) << "(HOLD " << escape_sdf_identifier(kv.first) << " (posedge " << escape_sdf_identifier(kv.second.second) << ") " << delay_triple.str() << ")\n";
721+
}
722+
os << indent(depth + 1) << ")\n"; //TIMINGCHECK
723+
}
724+
os << indent(depth) << ")\n"; //CELL
725+
}
729726
}
730727

731728
size_t find_port_size(std::string port_name) {
@@ -752,9 +749,9 @@ class BlackBoxInst : public Instance {
752749
std::map<std::string, std::vector<std::string>> input_port_conns_;
753750
std::map<std::string, std::vector<std::string>> output_port_conns_;
754751
std::vector<Arc> timing_arcs_;
755-
std::map<std::string, pair_d> ports_tsu_;
756-
std::map<std::string, pair_d> ports_thld_;
757-
std::map<std::string, pair_d> ports_tcq_;
752+
std::map<std::string, sequential_port_delay_pair> ports_tsu_;
753+
std::map<std::string, sequential_port_delay_pair> ports_thld_;
754+
std::map<std::string, sequential_port_delay_pair> ports_tcq_;
758755
};
759756

760757
/**
@@ -902,7 +899,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
902899
verilog_os_ << indent(depth + 1) << "wire " << escape_verilog_identifier(wire_tnode_pair.first) << ";\n";
903900
}
904901
}
905-
902+
906903
verilog_os_ << indent(depth + 1) << "wire DummyOut;\n";
907904

908905
//connections between primary I/Os and their internal wires
@@ -1288,9 +1285,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
12881285
std::map<std::string, std::vector<std::string>> input_port_conns;
12891286
std::map<std::string, std::vector<std::string>> output_port_conns;
12901287
std::vector<Arc> timing_arcs;
1291-
std::map<std::string, pair_d> ports_tsu;
1292-
std::map<std::string, pair_d> ports_thld;
1293-
std::map<std::string, pair_d> ports_tcq;
1288+
std::map<std::string, sequential_port_delay_pair> ports_tsu;
1289+
std::map<std::string, sequential_port_delay_pair> ports_thld;
1290+
std::map<std::string, sequential_port_delay_pair> ports_tcq;
12941291

12951292
params["ADDR_WIDTH"] = "0";
12961293
params["DATA_WIDTH"] = "0";
@@ -1382,7 +1379,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
13821379
"Unrecognized input port class '%s' for primitive '%s' (%s)\n", port_class.c_str(), atom->name, pb_type->name);
13831380
}
13841381
output_port_conns[port_name].push_back(net);
1385-
ports_tcq[port_name] = std::make_pair(pin->tco_max,pin->associated_clock_pin->port->name); //pin->tco_max;
1382+
ports_tcq[port_name] = std::make_pair(pin->tco_max, pin->associated_clock_pin->port->name);
13861383
}
13871384
}
13881385

@@ -1431,9 +1428,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
14311428
std::map<std::string, std::vector<std::string>> input_port_conns;
14321429
std::map<std::string, std::vector<std::string>> output_port_conns;
14331430
std::vector<Arc> timing_arcs;
1434-
std::map<std::string, pair_d> ports_tsu;
1435-
std::map<std::string, pair_d> ports_thld;
1436-
std::map<std::string, pair_d> ports_tcq;
1431+
std::map<std::string, sequential_port_delay_pair> ports_tsu;
1432+
std::map<std::string, sequential_port_delay_pair> ports_thld;
1433+
std::map<std::string, sequential_port_delay_pair> ports_tcq;
14371434

14381435
params["WIDTH"] = "0";
14391436

@@ -1527,9 +1524,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
15271524
std::map<std::string, std::vector<std::string>> input_port_conns;
15281525
std::map<std::string, std::vector<std::string>> output_port_conns;
15291526
std::vector<Arc> timing_arcs;
1530-
std::map<std::string, pair_d> ports_tsu;
1531-
std::map<std::string, pair_d> ports_thld;
1532-
std::map<std::string, pair_d> ports_tcq;
1527+
std::map<std::string, sequential_port_delay_pair> ports_tsu;
1528+
std::map<std::string, sequential_port_delay_pair> ports_thld;
1529+
std::map<std::string, sequential_port_delay_pair> ports_tcq;
15331530

15341531
params["WIDTH"] = "0";
15351532

@@ -1625,9 +1622,9 @@ class NetlistWriterVisitor : public NetlistVisitor {
16251622
std::map<std::string, std::vector<std::string>> input_port_conns;
16261623
std::map<std::string, std::vector<std::string>> output_port_conns;
16271624
std::vector<Arc> timing_arcs;
1628-
std::map<std::string, pair_d> ports_tsu;
1629-
std::map<std::string, pair_d> ports_thld;
1630-
std::map<std::string, pair_d> ports_tcq;
1625+
std::map<std::string, sequential_port_delay_pair> ports_tsu;
1626+
std::map<std::string, sequential_port_delay_pair> ports_thld;
1627+
std::map<std::string, sequential_port_delay_pair> ports_tcq;
16311628

16321629
//Delay matrix[sink_tnode] -> tuple of source_port_name, pin index, delay
16331630
std::map<tatum::NodeId, std::vector<std::tuple<std::string, int, double>>> tnode_delay_matrix;
@@ -1663,16 +1660,15 @@ class NetlistWriterVisitor : public NetlistVisitor {
16631660
}
16641661
}
16651662

1663+
input_port_conns[port->name].push_back(net);
1664+
if (pin->type == PB_PIN_SEQUENTIAL) {
1665+
if (!std::isnan(pin->tsu)) ports_tsu[port->name] = std::make_pair(pin->tsu, pin->associated_clock_pin->port->name);
1666+
if (!std::isnan(pin->thld)) ports_thld[port->name] = std::make_pair(pin->thld, pin->associated_clock_pin->port->name);
1667+
}
1668+
}
1669+
}
16661670

1667-
input_port_conns[port->name].push_back(net);
1668-
if (pin->type == PB_PIN_SEQUENTIAL) {
1669-
if (!std::isnan(pin->tsu)) ports_tsu[port->name] = std::make_pair(pin->tsu, pin->associated_clock_pin->port->name);
1670-
if (!std::isnan(pin->thld)) ports_thld[port->name] = std::make_pair(pin->thld, pin->associated_clock_pin->port->name);
1671-
}
1672-
}
1673-
}
1674-
1675-
//Process the output ports
1671+
//Process the output ports
16761672
for (int iport = 0; iport < pb_graph_node->num_output_ports; ++iport) {
16771673
for (int ipin = 0; ipin < pb_graph_node->num_output_pins[iport]; ++ipin) {
16781674
const t_pb_graph_pin* pin = &pb_graph_node->output_pins[iport][ipin];
@@ -1682,7 +1678,7 @@ class NetlistWriterVisitor : public NetlistVisitor {
16821678

16831679
std::string net;
16841680
if (!top_pb_route.count(cluster_pin_idx)) {
1685-
//Disconnected
1681+
//Disconnected
16861682
net = "";
16871683
} else {
16881684
//Connected
@@ -1700,9 +1696,8 @@ class NetlistWriterVisitor : public NetlistVisitor {
17001696
}
17011697
}
17021698

1703-
17041699
output_port_conns[port->name].push_back(net);
1705-
if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan(pin->tco_max)) ports_tcq[port->name] = std::make_pair(pin->tco_max,pin->associated_clock_pin->port->name);
1700+
if (pin->type == PB_PIN_SEQUENTIAL && !std::isnan(pin->tco_max)) ports_tcq[port->name] = std::make_pair(pin->tco_max, pin->associated_clock_pin->port->name);
17061701
}
17071702
}
17081703

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