add dummy ouput on usused outputs

tpagarani · acomodi · commit 3b7999e73214 · 2020-10-06T10:23:07.000+02:00
diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp
@@ -902,6 +902,8 @@ class NetlistWriterVisitor : public NetlistVisitor {
                 verilog_os_ << indent(depth + 1) << "wire " << escape_verilog_identifier(wire_tnode_pair.first) << ";\n";
             }
         }
+        
+        verilog_os_ << indent(depth + 1) << "wire DummyOut;\n";
 
         //connections between primary I/Os and their internal wires
         verilog_os_ << "\n";
@@ -2154,7 +2156,7 @@ void print_verilog_port(std::ostream& os, const std::string& port_name, const st
                 os << "1'b0";
             } else {
                 VTR_ASSERT(type == PortType::OUTPUT);
-                os << "";
+                os << "DummyOut";
             }
         } else {
             //Connected
@@ -2173,7 +2175,7 @@ void print_verilog_port(std::ostream& os, const std::string& port_name, const st
                     os << "1'b0";
                 } else {
                     VTR_ASSERT(type == PortType::OUTPUT);
-                    os << "";
+                    os << "DummyOut";
                 }
             } else {
                 //Connected

Original file line number	Diff line number	Diff line change
`@@ -902,6 +902,8 @@ class NetlistWriterVisitor : public NetlistVisitor {`
`902`	`902`	`verilog_os_ << indent(depth + 1) << "wire " << escape_verilog_identifier(wire_tnode_pair.first) << ";\n";`
`903`	`903`	`}`
`904`	`904`	`}`
	`905`	`+`
	`906`	`+ verilog_os_ << indent(depth + 1) << "wire DummyOut;\n";`
`905`	`907`
`906`	`908`	`//connections between primary I/Os and their internal wires`
`907`	`909`	`verilog_os_ << "\n";`
`@@ -2154,7 +2156,7 @@ void print_verilog_port(std::ostream& os, const std::string& port_name, const st`
`2154`	`2156`	`os << "1'b0";`
`2155`	`2157`	`} else {`
`2156`	`2158`	`VTR_ASSERT(type == PortType::OUTPUT);`
`2157`		`- os << "";`
	`2159`	`+ os << "DummyOut";`
`2158`	`2160`	`}`
`2159`	`2161`	`} else {`
`2160`	`2162`	`//Connected`
`@@ -2173,7 +2175,7 @@ void print_verilog_port(std::ostream& os, const std::string& port_name, const st`
`2173`	`2175`	`os << "1'b0";`
`2174`	`2176`	`} else {`
`2175`	`2177`	`VTR_ASSERT(type == PortType::OUTPUT);`
`2176`		`- os << "";`
	`2178`	`+ os << "DummyOut";`
`2177`	`2179`	`}`
`2178`	`2180`	`} else {`
`2179`	`2181`	`//Connected`