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Merge pull request #2472 from verilog-to-routing/fix_3d_arch
Fix: Address warnings in Koios 3D architectures and add additional test
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‎vtr_flow/arch/multi_die/README.md

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@@ -6,6 +6,7 @@ This directory contains architecture files for 3D FPGAs. The architectures are d
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- Contains architecture files based on the [k6FracN10LB_mem20K_complexDSP_customSB_22nm](../COFFE_22nm/k6FracN10LB_mem20K_complexDSP_customSB_22nm.clustered.xml) architecture, utilized in Koios benchmarks.
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- Inside the architecture file, the fabric with multiple sizes based on the sector size is defined.
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- Routing resource and switch delays in this architecture are configured for 7 nm technology. The inter-die connection delay is 73 ps.
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- The empty blocks in the middle of the fabric at the base die, which have the chess pattern, represent the through-silicon via (TSV) holes used to deliver power and ground to the upper die.
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- Detailed information on how these delays are obtained can be found in the paper "Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices," presented at FPT '23.
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- **Architectures:**
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- `3d_full_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml`

‎vtr_flow/arch/multi_die/koios_3d/3d_full_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml

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@@ -221,16 +221,6 @@
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="tsv_hole" height="2" width="2" area="137668">
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<sub_tile name="tsv_hole">
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<equivalent_sites>
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<site pb_type="tsv_hole"/>
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</equivalent_sites>
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<input name="in" num_pins="1"/>
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<output name="out" num_pins="1"/>
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<fc in_type="abs" in_val="0" out_type="abs" out_val="0"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<layout>
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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</pb_type>
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<!-- Define fracturable memory end -->
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<pb_type name="tsv_hole">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<interconnect/>
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</pb_type>
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</complexblocklist>
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<switchblocklist>

‎vtr_flow/arch/multi_die/koios_3d/3d_limited_OPIN_inter_die_k6FracN10LB_mem20k_complexDSP_customSB_7nm.xml

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@@ -212,16 +212,6 @@
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="tsv_hole" height="2" width="2" area="137668">
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<sub_tile name="tsv_hole">
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<equivalent_sites>
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<site pb_type="tsv_hole"/>
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</equivalent_sites>
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<input name="in" num_pins="1"/>
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<output name="out" num_pins="1"/>
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<fc in_type="abs" in_val="0" out_type="abs" out_val="0"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<layout>
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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<col type="dsp_top" startx="31" starty="1" repeatx="41" priority="20"/>
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<!-- PW -->
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<col type="tsv_hole" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="8" starty="5" repeatx="13" incry="12" priority="103"/>
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<!-- GND -->
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<col type="tsv_hole" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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<col type="EMPTY" startx="14" starty="11" repeatx="13" incry="12" priority="103"/>
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</layer>
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<layer die="1">
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</mode>
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</pb_type>
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<!-- Define fracturable memory end -->
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<pb_type name="tsv_hole">
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<input name="I" num_pins="1"/>
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<output name="O" num_pins="1"/>
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<interconnect/>
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</pb_type>
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</complexblocklist>
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<switchblocklist>

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/config.txt renamed to ‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_auto_bb/config/config.txt

File renamed without changes.

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other/config/golden_results.txt renamed to ‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_auto_bb/config/golden_results.txt

File renamed without changes.

‎vtr_flow/tasks/regression_tests/vtr_reg_nightly_test7/3d_titan_other_full_opin_cube_bb/config/config.txt

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#
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############################################
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# Configuration file for running experiments
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##############################################
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# Path to directory of circuits to use
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circuits_dir=benchmarks/titan_blif/other_benchmarks/stratixiv
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# Path to directory of SDC files
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sdc_dir=benchmarks/titan_blif/other_benchmarks/stratixiv
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# Path to directory of architectures to use
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archs_dir=arch/multi_die/stratixiv_3d
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# Add circuits to list to sweep
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circuit_list_add=carpat_stratixiv_arch_timing.blif
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circuit_list_add=CH_DFSIN_stratixiv_arch_timing.blif
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circuit_list_add=CHERI_stratixiv_arch_timing.blif
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circuit_list_add=EKF-SLAM_Jacobians_stratixiv_arch_timing.blif
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circuit_list_add=fir_cascade_stratixiv_arch_timing.blif
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circuit_list_add=jacobi_stratixiv_arch_timing.blif
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circuit_list_add=JPEG_stratixiv_arch_timing.blif
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circuit_list_add=leon2_stratixiv_arch_timing.blif
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circuit_list_add=leon3mp_stratixiv_arch_timing.blif
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circuit_list_add=MCML_stratixiv_arch_timing.blif
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circuit_list_add=MMM_stratixiv_arch_timing.blif
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circuit_list_add=radar20_stratixiv_arch_timing.blif
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circuit_list_add=random_stratixiv_arch_timing.blif
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circuit_list_add=Reed_Solomon_stratixiv_arch_timing.blif
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circuit_list_add=smithwaterman_stratixiv_arch_timing.blif
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circuit_list_add=stap_steering_stratixiv_arch_timing.blif
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circuit_list_add=sudoku_check_stratixiv_arch_timing.blif
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circuit_list_add=SURF_desc_stratixiv_arch_timing.blif
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circuit_list_add=ucsb_152_tap_fir_stratixiv_arch_timing.blif
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circuit_list_add=uoft_raytracer_stratixiv_arch_timing.blif
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circuit_list_add=wb_conmax_stratixiv_arch_timing.blif
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circuit_list_add=picosoc_stratixiv_arch_timing.blif
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circuit_list_add=murax_stratixiv_arch_timing.blif
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# Add architectures to list to sweep
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arch_list_add=3d_full_OPIN_inter_die_stratixiv_arch.timing.xml
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# Parse info and how to parse
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parse_file=vpr_titan.txt
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# How to parse QoR info
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qor_parse_file=qor_vpr_titan.txt
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# Pass requirements
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pass_requirements_file=pass_requirements_vpr_titan.txt
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script_params=-starting_stage vpr --route_chan_width 300 --max_router_iterations 400 --router_lookahead map --place_bounding_box_mode cube_bb

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