replace calls to is_io_type() with t_physical_tile_type::is_io()

Author: soheilshahrouz

libs/libarchfpga/src/physical_types.cpp

@@ -172,7 +172,7 @@ bool t_physical_tile_type::is_empty() const {
     return name == std::string(EMPTY_BLOCK_NAME);
 }
 
-bool t_physical_tile_type::is_io_type() const {
+bool t_physical_tile_type::is_io() const {
     return is_input_type || is_output_type;
 }
 

libs/libarchfpga/src/physical_types.h

@@ -726,7 +726,7 @@ struct t_physical_tile_type {
     bool is_empty() const;
 
     ///@brief Returns true if the physical tile type can implement either a .input or .output block type
-    bool is_io_type() const;
+    bool is_io() const;
 
     ///@brief Returns the relative pin index within a sub tile that corresponds to the pin within the given port and its index in the port
     int find_pin(std::string_view port_name, int pin_index_in_port) const;

vpr/src/base/ShowSetup.cpp

@@ -135,7 +135,7 @@ ClusteredNetlistStats::ClusteredNetlistStats() {
         auto logical_block = cluster_ctx.clb_nlist.block_type(blk_id);
         auto physical_tile = pick_physical_type(logical_block);
         num_blocks_type[logical_block->index]++;
-        if (is_io_type(physical_tile)) {
+        if (physical_tile->is_io()) {
             for (int j = 0; j < logical_block->pb_type->num_pins; j++) {
                 int physical_pin = get_physical_pin(physical_tile, logical_block, j);
 

vpr/src/base/check_netlist.cpp

@@ -110,8 +110,7 @@ static int check_connections_to_global_clb_pins(ClusterNetId net_id, int verbosi
         int log_index = cluster_ctx.clb_nlist.pin_logical_index(pin_id);
         int pin_index = get_physical_pin(physical_type, logical_type, log_index);
 
-        if (physical_type->is_ignored_pin[pin_index] != net_is_ignored
-            && !is_io_type(physical_type)) {
+        if (physical_type->is_ignored_pin[pin_index] != net_is_ignored && !physical_type->is_io()) {
             VTR_LOGV_WARN(verbosity > 2,
                           "Global net '%s' connects to non-global architecture pin '%s' (netlist pin '%s')\n",
                           cluster_ctx.clb_nlist.net_name(net_id).c_str(),

vpr/src/base/read_route.cpp

@@ -296,7 +296,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN
             /* Verify types and ptc*/
             if (tokens[2] == "SOURCE" || tokens[2] == "SINK" || tokens[2] == "OPIN" || tokens[2] == "IPIN") {
                 const auto& type = device_ctx.grid.get_physical_type({x, y, layer_num});
-                if (tokens[4 + offset] == "Pad:" && !is_io_type(type)) {
+                if (tokens[4 + offset] == "Pad:" && !type->is_io()) {
                     vpr_throw(VPR_ERROR_ROUTE, filename, lineno,
                               "Node %d is of the wrong type", inode);
                 }
@@ -319,7 +319,7 @@ static void process_nodes(const Netlist<>& net_list, std::ifstream& fp, ClusterN
             if (tokens[6 + offset] != "Switch:") {
                 /*This is an opin or ipin, process its pin nums*/
                 auto type = device_ctx.grid.get_physical_type({x, y, layer_num});
-                if (!is_io_type(type) && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) {
+                if (!type->is_io() && (tokens[2] == "IPIN" || tokens[2] == "OPIN")) {
                     int pin_num = rr_graph.node_pin_num(RRNodeId(inode));
                     int width_offset = device_ctx.grid.get_width_offset({x, y, layer_num});
                     int height_offset = device_ctx.grid.get_height_offset({x, y, layer_num});
@@ -592,10 +592,13 @@ void print_route(const Netlist<>& net_list,
                         fprintf(fp, "to (%d,%d,%d) ", rr_graph.node_xhigh(inode),
                                 rr_graph.node_yhigh(inode), layer_num);
 
+                    t_physical_tile_type_ptr physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num});
+
                     switch (rr_type) {
                         case e_rr_type::IPIN:
                         case e_rr_type::OPIN:
-                            if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) {
+
+                            if (physical_tile->is_io()) {
                                 fprintf(fp, " Pad: ");
                             } else { /* IO Pad. */
                                 fprintf(fp, " Pin: ");
@@ -609,7 +612,7 @@ void print_route(const Netlist<>& net_list,
 
                         case e_rr_type::SOURCE:
                         case e_rr_type::SINK:
-                            if (is_io_type(device_ctx.grid.get_physical_type({ilow, jlow, layer_num}))) {
+                            if (physical_tile->is_io()) {
                                 fprintf(fp, " Pad: ");
                             } else { /* IO Pad. */
                                 fprintf(fp, " Class: ");
@@ -625,8 +628,8 @@ void print_route(const Netlist<>& net_list,
 
                     fprintf(fp, "%d  ", rr_graph.node_ptc_num(inode));
 
-                    auto physical_tile = device_ctx.grid.get_physical_type({ilow, jlow, layer_num});
-                    if (!is_io_type(physical_tile) && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) {
+
+                    if (!physical_tile->is_io() && (rr_type == e_rr_type::IPIN || rr_type == e_rr_type::OPIN)) {
                         int pin_num = rr_graph.node_pin_num(inode);
                         int xoffset = device_ctx.grid.get_width_offset({ilow, jlow, layer_num});
                         int yoffset = device_ctx.grid.get_height_offset({ilow, jlow, layer_num});

vpr/src/base/stats.cpp

@@ -91,10 +91,7 @@ void routing_stats(const Netlist<>& net_list,
                 auto type = device_ctx.grid.get_physical_type({i, j, layer_num});
                 int width_offset = device_ctx.grid.get_width_offset({i, j, layer_num});
                 int height_offset = device_ctx.grid.get_height_offset({i, j, layer_num});
-                if (width_offset == 0
-                    && height_offset == 0
-                    && !is_io_type(type)
-                    && type != device_ctx.EMPTY_PHYSICAL_TILE_TYPE) {
+                if (width_offset == 0 && height_offset == 0 && !type->is_io() && !type->is_empty()) {
                     if (type->area == UNDEFINED) {
                         area += grid_logic_tile_area * type->width * type->height;
                     } else {
@@ -111,7 +108,7 @@ void routing_stats(const Netlist<>& net_list,
     for (ClusterBlockId blk_id : cluster_ctx.clb_nlist.blocks()) {
         t_pl_loc block_loc = block_locs[blk_id].loc;
         auto type = physical_tile_type(block_loc);
-        if (!is_io_type(type)) {
+        if (!type->is_io()) {
             if (type->area == UNDEFINED) {
                 used_area += grid_logic_tile_area * type->width * type->height;
             } else {
@@ -473,7 +470,7 @@ void print_lambda() {
         t_pl_loc block_loc = block_locs[blk_id].loc;
         auto type = physical_tile_type(block_loc);
         VTR_ASSERT(type != nullptr);
-        if (!is_io_type(type)) {
+        if (!type->is_io()) {
             for (int ipin = 0; ipin < type->num_pins; ipin++) {
                 if (get_pin_type_from_pin_physical_num(type, ipin) == RECEIVER) {
                     ClusterNetId net_id = cluster_ctx.clb_nlist.block_net(blk_id, ipin);

vpr/src/pack/appack_max_dist_th_manager.cpp

@@ -100,7 +100,7 @@ void APPackMaxDistThManager::auto_set_max_distance_thresholds(const std::vector<
         // Find which type(s) this logical block type looks like.
         bool has_memory = has_memory_pbs(lb_ty.pb_type);
         bool is_logic_block_type = (lb_ty.index == logic_block_type->index);
-        bool is_io_block = is_io_type(pick_physical_type(&lb_ty));
+        bool is_io_block = pick_physical_type(&lb_ty)->is_io();
 
         // Update the max distance threshold based on the type. If the logical
         // block type looks like many block types at the same time (for example

vpr/src/place/initial_placement.cpp

@@ -1012,10 +1012,10 @@ static inline void fix_IO_block_types(const t_pl_macro& pl_macro,
                                       vtr::vector_map<ClusterBlockId, t_block_loc>& block_locs) {
     const auto& device_ctx = g_vpr_ctx.device();
 
-    //If the user marked the IO block pad_loc_type as RANDOM, that means it should be randomly
-    //placed and then stay fixed to that location, which is why the macro members are marked as fixed.
-    const auto& type = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer});
-    if (is_io_type(type) && pad_loc_type == e_pad_loc_type::RANDOM) {
+    // If the user marked the IO block pad_loc_type as RANDOM, that means it should be randomly
+    // placed and then stay fixed to that location, which is why the macro members are marked as fixed.
+    const t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({loc.x, loc.y, loc.layer});
+    if (type->is_io() && pad_loc_type == e_pad_loc_type::RANDOM) {
         for (const t_pl_macro_member& pl_macro_member : pl_macro.members) {
             block_locs[pl_macro_member.blk_index].is_fixed = true;
         }

vpr/src/route/route_common.cpp

@@ -358,7 +358,7 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() {
 
         clb_opins_used_locally[blk_id].resize((int)type->class_inf.size());
 
-        if (is_io_type(type)) continue;
+        if (type->is_io()) continue;
 
         const auto [pin_low, pin_high] = get_pin_range_for_block(blk_id);
 

vpr/src/route/rr_graph_generation/rr_node_indices.cpp

@@ -4,6 +4,7 @@
 #include "describe_rr_node.h"
 #include "globals.h"
 #include "physical_types_util.h"
+#include "vpr_utils.h"
 
 /**
  * @brief Assigns and loads rr_node indices for block-level routing resources (SOURCE, SINK, IPIN, OPIN).
@@ -70,15 +71,15 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder,
 static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder,
                                   const DeviceGrid& grid,
                                   int* index) {
-    //Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN
+    // Walk through the grid assigning indices to SOURCE/SINK IPIN/OPIN
     for (int layer = 0; layer < grid.get_num_layers(); layer++) {
         for (int x = 0; x < (int)grid.width(); x++) {
             for (int y = 0; y < (int)grid.height(); y++) {
                 //Process each block from its root location
                 if (grid.is_root_location({x, y, layer})) {
                     t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer});
 
-                    //Assign indices for SINKs and SOURCEs
+                    // Assign indices for SINKs and SOURCEs
                     // Note that SINKS/SOURCES have no side, so we always use side 0
                     std::vector<int> class_num_vec = get_tile_root_classes(physical_type);
                     std::vector<int> pin_num_vec = get_tile_root_pins(physical_type);
@@ -124,22 +125,20 @@ static void load_block_rr_indices(RRGraphBuilder& rr_graph_builder,
                      *   for the same input pin on multiple sides, and thus avoid multiple driver problems
                      */
                     std::vector<e_side> wanted_sides;
-                    if ((int)grid.height() - 1 == y) { /* TOP side */
+                    if ((int)grid.height() - 1 == y) { // TOP side
                         wanted_sides.push_back(BOTTOM);
                     }
-                    if ((int)grid.width() - 1 == x) { /* RIGHT side */
+                    if ((int)grid.width() - 1 == x) { // RIGHT side
                         wanted_sides.push_back(LEFT);
                     }
-                    if (0 == y) { /* BOTTOM side */
+                    if (0 == y) { // BOTTOM side
                         wanted_sides.push_back(TOP);
                     }
-                    if (0 == x) { /* LEFT side */
+                    if (0 == x) { // LEFT side
                         wanted_sides.push_back(RIGHT);
                     }
 
-                    /* If wanted sides is empty still, this block does not have specific wanted sides,
-                     * Deposit all the sides
-                     */
+                    // If wanted sides is empty still, this block does not have specific wanted sides, Deposit all the sides
                     if (wanted_sides.empty()) {
                         for (e_side side : TOTAL_2D_SIDES) {
                             wanted_sides.push_back(side);
@@ -262,7 +261,7 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder,
             int x_tile = root_x + width_offset;
             for (int height_offset = 0; height_offset < physical_type_ptr->height; ++height_offset) {
                 int y_tile = root_y + height_offset;
-                //only nodes on the tile may be located in a location other than the root-location
+                // only nodes on the tile may be located in a location other than the root-location
                 rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::OPIN, physical_type_ptr->num_pins, side);
                 rr_graph_builder.node_lookup().reserve_nodes(layer, x_tile, y_tile, e_rr_type::IPIN, physical_type_ptr->num_pins, side);
             }
@@ -309,15 +308,15 @@ void alloc_and_load_rr_node_indices(RRGraphBuilder& rr_graph_builder,
                                     int* index,
                                     const t_chan_details& chan_details_x,
                                     const t_chan_details& chan_details_y) {
-    /* Alloc the lookup table */
+    // Alloc the lookup table
     for (e_rr_type rr_type : RR_TYPES) {
         rr_graph_builder.node_lookup().resize_nodes(grid.get_num_layers(), grid.width(), grid.height(), rr_type, NUM_2D_SIDES);
     }
 
-    /* Assign indices for block nodes */
+    // Assign indices for block nodes
     load_block_rr_indices(rr_graph_builder, grid, index);
 
-    /* Load the data for x and y channels */
+    // Load the data for x and y channels
     load_chan_rr_indices(nodes_per_chan.x_max, grid, grid.width(), grid.height(),
                          e_rr_type::CHANX, chan_details_x, rr_graph_builder.node_lookup(), index);
     load_chan_rr_indices(nodes_per_chan.y_max, grid, grid.height(), grid.width(),
@@ -341,7 +340,7 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder,
     const auto& device_ctx = g_vpr_ctx.device();
 
     for (int layer = 0; layer < grid.get_num_layers(); layer++) {
-        /* Skip the current die if architecture file specifies that it doesn't have global resource routing */
+        // Skip the current die if architecture file specifies that it doesn't have global resource routing
         if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) {
             continue;
         }
@@ -412,10 +411,10 @@ void alloc_and_load_intra_cluster_rr_node_indices(RRGraphBuilder& rr_graph_build
     for (int layer = 0; layer < grid.get_num_layers(); layer++) {
         for (int x = 0; x < (int)grid.width(); x++) {
             for (int y = 0; y < (int)grid.height(); y++) {
-                //Process each block from its root location
+                // Process each block from its root location
                 if (grid.is_root_location({x, y, layer})) {
                     t_physical_tile_type_ptr physical_type = grid.get_physical_type({x, y, layer});
-                    //Assign indices for SINKs and SOURCEs
+                    // Assign indices for SINKs and SOURCEs
                     // Note that SINKS/SOURCES have no side, so we always use side 0
                     std::vector<int> class_num_vec;
                     std::vector<int> pin_num_vec;
@@ -467,7 +466,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid,
         for (int x = 0; x < width; ++x) {
             for (int y = 0; y < height; ++y) {
                 for (e_rr_type rr_type : RR_TYPES) {
-                    /* Get the list of nodes at a specific location (x, y) */
+                    // Get the list of nodes at a specific location (x, y)
                     std::vector<RRNodeId> nodes_from_lookup;
                     if (rr_type == e_rr_type::CHANX || rr_type == e_rr_type::CHANY) {
                         nodes_from_lookup = rr_graph.node_lookup().find_channel_nodes(l, x, y, rr_type);
@@ -584,7 +583,7 @@ bool verify_rr_node_indices(const DeviceGrid& grid,
         RRNodeId inode = kv.first;
         int count = kv.second;
 
-        auto& rr_node = rr_nodes[size_t(inode)];
+        const t_rr_node& rr_node = rr_nodes[size_t(inode)];
 
         if (rr_graph.node_type(inode) == e_rr_type::SOURCE || rr_graph.node_type(inode) == e_rr_type::SINK) {
             int rr_width = (rr_graph.node_xhigh(rr_node.id()) - rr_graph.node_xlow(rr_node.id()) + 1);
@@ -597,9 +596,9 @@ bool verify_rr_node_indices(const DeviceGrid& grid,
                           count,
                           describe_rr_node(rr_graph, grid, rr_indexed_data, inode, is_flat).c_str());
             }
-            /* As we allow a pin to be indexable on multiple sides,
-             * This check code should not be applied to input and output pins
-             */
+            // As we allow a pin to be indexable on multiple sides,
+            // This check code should not be applied to input and output pins
+
         } else if ((e_rr_type::OPIN != rr_graph.node_type(inode)) && (e_rr_type::IPIN != rr_graph.node_type(inode))) {
             if (count != rr_node.length() + 1) {
                 VPR_ERROR(VPR_ERROR_ROUTE, "Mismatch between RR node length (%d) and count within rr_node_indices (%d, should be length + 1): %s",

vpr/src/util/vpr_utils.h

@@ -286,13 +286,6 @@ std::vector<int> get_cluster_netlist_intra_tile_classes_at_loc(int layer,
 
 /**
  * @brief Returns the list of pins inside the tile located at (layer, i, j), except for the ones which are on a chain
- * @param layer
- * @param i
- * @param j
- * @param pin_chains
- * @param pin_chains_num
- * @param physical_type
- * @return
  */
 std::vector<int> get_cluster_netlist_intra_tile_pins_at_loc(const int layer,
                                                             const int i,