[test] add new test

Author: tangxifan

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/config.txt

@@ -0,0 +1,29 @@
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=benchmarks/blif/4
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=diffeq.blif
+circuit_list_add=ex5p.blif
+circuit_list_add=s298.blif
+
+# Add architectures to list to sweep
+arch_list_add=k4_N4_tileable_perimeter_cb_90nm.xml
+ 
+# Parse info and how to parse
+parse_file=vpr_standard.txt
+
+# How to parse QoR info
+qor_parse_file=qor_standard.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements.txt
+
+script_params=-starting_stage vpr -track_memory_usage
+

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb/config/golden_results.txt

@@ -0,0 +1,4 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	yosys_synth_time	max_yosys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	placed_wirelength_est	place_mem	place_time	place_quench_time	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	min_chan_width	routed_wirelength	min_chan_width_route_success_iteration	logic_block_area_total	logic_block_area_used	min_chan_width_routing_area_total	min_chan_width_routing_area_per_tile	min_chan_width_route_time	min_chan_width_total_timing_analysis_time	min_chan_width_total_sta_time	crit_path_routed_wirelength	crit_path_route_success_iteration	crit_path_total_nets_routed	crit_path_total_connections_routed	crit_path_total_heap_pushes	crit_path_total_heap_pops	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	crit_path_routing_area_total	crit_path_routing_area_per_tile	router_lookahead_computation_time	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	
+k4_N4_tileable_90nm.xml	diffeq.blif	common	9.82	vpr	61.45 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	417	64	-1	-1	success	v8.0.0-6725-gff83963de-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64	2022-11-01T15:38:22	LAPTOP-CVNHOGSN	/home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks	62920	64	39	1935	1974	1	1104	520	23	23	529	clb	auto	18.8 MiB	0.14	10227	61.2 MiB	0.57	0.01	6.71028	-1587.65	-6.71028	6.71028	0.25	0.0007736	0.0005813	0.0896507	0.0699632	34	17207	50	983127	929624	921133.	1741.27	7.25	0.536827	0.433199	14874	22	8645	29434	2727679	902790	6.8984	6.8984	-1779.84	-6.8984	0	0	1.17586e+06	2222.80	0.07	0.39	0.058014	0.0505961	
+k4_N4_tileable_90nm.xml	ex5p.blif	common	15.22	vpr	52.07 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	346	8	-1	-1	success	v8.0.0-6725-gff83963de-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64	2022-11-01T15:38:22	LAPTOP-CVNHOGSN	/home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks	53324	8	63	1072	1135	0	909	417	21	21	441	clb	auto	14.2 MiB	0.10	11660	52.1 MiB	0.46	0.00	7.1886	-311.061	-7.1886	nan	0.20	0.000496	0.0003719	0.0573232	0.0458367	56	22886	46	804782	771343	1.13430e+06	2572.11	12.88	0.310125	0.253318	18533	21	8880	28500	4332796	1534540	7.97924	nan	-339.269	-7.97924	0	0	1.45200e+06	3292.52	0.08	0.50	0.0368923	0.0322975	
+k4_N4_tileable_90nm.xml	s298.blif	common	21.05	vpr	75.85 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	571	4	-1	-1	success	v8.0.0-6725-gff83963de-dirty	release IPO VTR_ASSERT_LEVEL=2	GNU 9.3.0 on Linux-4.4.0-19041-Microsoft x86_64	2022-11-01T15:38:22	LAPTOP-CVNHOGSN	/home/tangxifan/vtr-verilog-to-routing/vtr_flow/tasks	77672	4	6	1942	1948	1	1193	581	26	26	676	clb	auto	21.3 MiB	0.14	14254	75.9 MiB	0.69	0.01	13.2884	-103	-13.2884	13.2884	0.33	0.0008181	0.0006197	0.0966404	0.0764946	42	26119	42	1.28409e+06	1.27294e+06	1.41510e+06	2093.35	17.58	0.615507	0.493511	22147	19	9442	45483	4771423	1297512	13.6006	13.6006	-107.558	-13.6006	0	0	1.86822e+06	2763.64	0.19	0.67	0.0640435	0.0560669