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[test] add perimeter_cb to strong test
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‎vtr_flow/arch/timing/k4_N4_tileable_perimeter_cb_90nm.xml

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<!--
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Architecture file translated from ifar repository N04K04L01.FC15FO25.AREA1DELAY1.CMOS90NM.BPTM
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Simple architecture file consisting of clusters of 4 BLEs, each BLE contains a 4-LUT+FF pair. Delay models from 90nm PTM.
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-->
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<architecture>
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<!--
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ODIN II specific config begins
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Describes the types of user-specified netlist blocks (in blif, this corresponds to
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".model [type_of_block]") that this architecture supports.
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Note: Basic LUTs, I/Os, and flip-flops are not included here as there are
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already special structures in blif (.names, .input, .output, and .latch)
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that describe them.
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-->
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<models>
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</models>
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<tiles>
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<tile name="io">
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<sub_tile name="io" capacity="3">
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<equivalent_sites>
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<site pb_type="io" pin_mapping="direct"/>
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</equivalent_sites>
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<fc in_type="frac" in_val="1.0" out_type="frac" out_val="0.25"/>
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<pinlocations pattern="custom">
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<loc side="left">io.outpad io.inpad io.clock</loc>
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<loc side="top">io.outpad io.inpad io.clock</loc>
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<loc side="right">io.outpad io.inpad io.clock</loc>
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<loc side="bottom">io.outpad io.inpad io.clock</loc>
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</pinlocations>
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</sub_tile>
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</tile>
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<tile name="clb">
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<sub_tile name="clb">
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<equivalent_sites>
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<site pb_type="clb" pin_mapping="direct"/>
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</equivalent_sites>
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<input name="I" num_pins="10" equivalent="full"/>
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<output name="O" num_pins="4" equivalent="instance"/>
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<clock name="clk" num_pins="1"/>
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<fc in_type="frac" in_val="0.15" out_type="frac" out_val="0.25"/>
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<pinlocations pattern="spread"/>
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</sub_tile>
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</tile>
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</tiles>
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<!-- ODIN II specific config ends -->
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<!-- Physical descriptions begin -->
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<layout tileable="true" perimeter_cb="true">
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<auto_layout aspect_ratio="1.000000">
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<!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
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<perimeter type="io" priority="100"/>
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<corners type="EMPTY" priority="101"/>
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<!--Fill with 'clb'-->
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<fill type="clb" priority="10"/>
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</auto_layout>
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</layout>
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<device>
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<sizing R_minW_nmos="4220.930176" R_minW_pmos="11207.599609"/>
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<area grid_logic_tile_area="2229.320068"/>
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<chan_width_distr>
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<x distr="uniform" peak="1.000000"/>
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<y distr="uniform" peak="1.000000"/>
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</chan_width_distr>
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<switch_block type="wilton" fs="3"/>
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<connection_block input_switch_name="ipin_cblock"/>
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</device>
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<switchlist>
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<switch type="mux" name="0" R="0.000000" Cin="0.000000e+00" Cout="0.000000e+00" Tdel="6.244000e-11" mux_trans_size="1.835460" buf_size="10.498600"/>
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<!--switch ipin_cblock resistance set to yeild for 4x minimum drive strength buffer-->
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<switch type="mux" name="ipin_cblock" R="1055.232544" Cout="0." Cin="0.000000e+00" Tdel="8.045000e-11" mux_trans_size="0.983352" buf_size="auto"/>
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</switchlist>
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<segmentlist>
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<segment freq="0.500000" length="1" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
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<mux name="0"/>
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<sb type="pattern">1 1</sb>
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<cb type="pattern">1</cb>
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</segment>
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<segment freq="0.500000" length="4" type="unidir" Rmetal="0.000000" Cmetal="0.000000e+00">
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<mux name="0"/>
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<sb type="pattern">1 1 1 1 1</sb>
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<cb type="pattern">1 1 1 1</cb>
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</segment>
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</segmentlist>
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<complexblocklist>
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<!-- Define I/O pads begin -->
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<!-- Capacity is a unique property of I/Os, it is the maximum number of I/Os that can be placed at the same (X,Y) location on the FPGA -->
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<pb_type name="io">
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<input name="outpad" num_pins="1"/>
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<output name="inpad" num_pins="1"/>
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<clock name="clock" num_pins="1"/>
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<!-- IOs can operate as either inputs or outputs.
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Delays below come from Ian Kuon. They are small, so they should be interpreted as
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the delays to and from registers in the I/O (and generally I/Os are registered
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today and that is when you timing analyze them.
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-->
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<mode name="inpad">
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<pb_type name="inpad" blif_model=".input" num_pb="1">
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<output name="inpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="inpad" input="inpad.inpad" output="io.inpad">
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<delay_constant max="9.492000e-11" in_port="inpad.inpad" out_port="io.inpad"/>
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</direct>
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</interconnect>
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</mode>
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<mode name="outpad">
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<pb_type name="outpad" blif_model=".output" num_pb="1">
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<input name="outpad" num_pins="1"/>
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</pb_type>
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<interconnect>
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<direct name="outpad" input="io.outpad" output="outpad.outpad">
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<delay_constant max="2.675000e-11" in_port="io.outpad" out_port="outpad.outpad"/>
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</direct>
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</interconnect>
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</mode>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 10% of the tracks in a channel -->
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<!-- IOs go on the periphery of the FPGA, for consistency,
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make it physically equivalent on all sides so that only one definition of I/Os is needed.
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If I do not make a physically equivalent definition, then I need to define 4 different I/Os, one for each side of the FPGA
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-->
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<!-- Place I/Os on the sides of the FPGA -->
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<power method="ignore"/>
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</pb_type>
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<!-- Define I/O pads ends -->
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<!-- Define general purpose logic block (CLB) begin -->
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<pb_type name="clb">
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<input name="I" num_pins="10" equivalent="full"/>
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<output name="O" num_pins="4" equivalent="instance"/>
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<clock name="clk" num_pins="1"/>
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<!-- Describe basic logic element. -->
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<pb_type name="fle" num_pb="4">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- 4-LUT mode definition begin -->
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<mode name="n1_lut4">
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<!-- Define 4-LUT mode -->
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<pb_type name="ble4" num_pb="1">
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<input name="in" num_pins="4"/>
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<output name="out" num_pins="1"/>
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<clock name="clk" num_pins="1"/>
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<!-- Define LUT -->
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<pb_type name="lut4" blif_model=".names" num_pb="1" class="lut">
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<input name="in" num_pins="4" port_class="lut_in"/>
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<output name="out" num_pins="1" port_class="lut_out"/>
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<!-- LUT timing using delay matrix -->
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<delay_matrix type="max" in_port="lut4.in" out_port="lut4.out">
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2.253000e-10
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2.253000e-10
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2.253000e-10
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2.253000e-10
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</delay_matrix>
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</pb_type>
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<!-- Define flip-flop -->
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<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop">
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<input name="D" num_pins="1" port_class="D"/>
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<output name="Q" num_pins="1" port_class="Q"/>
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<clock name="clk" num_pins="1" port_class="clock"/>
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<T_setup value="2.160000e-10" port="ff.D" clock="clk"/>
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<T_clock_to_Q max="1.426000e-10" port="ff.Q" clock="clk"/>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="ble4.in" output="lut4[0:0].in"/>
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<direct name="direct2" input="lut4.out" output="ff.D">
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<!-- Advanced user option that tells CAD tool to find LUT+FF pairs in netlist -->
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<pack_pattern name="ble6" in_port="lut4.out" out_port="ff.D"/>
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</direct>
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<direct name="direct3" input="ble4.clk" output="ff.clk"/>
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<mux name="mux1" input="ff.Q lut4.out" output="ble4.out">
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</mux>
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</interconnect>
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</pb_type>
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<interconnect>
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<direct name="direct1" input="fle.in" output="ble4.in"/>
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<direct name="direct2" input="ble4.out" output="fle.out[0:0]"/>
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<direct name="direct3" input="fle.clk" output="ble4.clk"/>
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</interconnect>
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</mode>
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<!-- 4-LUT mode definition end -->
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</pb_type>
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<interconnect>
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<!-- We use a full crossbar to get logical equivalence at inputs of CLB -->
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<complete name="crossbar" input="clb.I fle[3:0].out" output="fle[3:0].in">
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<delay_constant max="5.735000e-11" in_port="clb.I" out_port="fle[3:0].in"/>
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<delay_constant max="5.428000e-11" in_port="fle[3:0].out" out_port="fle[3:0].in"/>
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</complete>
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<complete name="clks" input="clb.clk" output="fle[3:0].clk">
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</complete>
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<direct name="clbouts1" input="fle[3:0].out" output="clb.O"/>
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</interconnect>
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<!-- Every input pin is driven by 15% of the tracks in a channel, every output pin is driven by 25% of the tracks in a channel -->
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<!-- Place this general purpose logic block in any unspecified column -->
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</pb_type>
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<!-- Define general purpose logic block (CLB) ends -->
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</complexblocklist>
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</architecture>

‎vtr_flow/tasks/regression_tests/vtr_reg_strong/task_list.txt

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@@ -84,8 +84,9 @@ regression_tests/vtr_reg_strong/strong_timing_fail
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regression_tests/vtr_reg_strong/strong_timing_no_fail
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regression_tests/vtr_reg_strong/strong_vpr_constraint
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regression_tests/vtr_reg_strong/strong_tileable_rr_graph
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regression_tests/vtr_reg_strong/strong_tileable_rr_graph_perimeter_cb
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regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify
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regression_tests/vtr_reg_strong/strong_tileable_rr_graph_verify_bin
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regression_tests/vtr_reg_strong/strong_noc
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regression_tests/vtr_reg_strong/strong_flat_router
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regression_tests/vtr_reg_strong/strong_routing_constraints
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regression_tests/vtr_reg_strong/strong_routing_constraints

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