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[Infra]: make VTR benchmarks compatible with Yosys+Odin
Signed-off-by: Seyed Alireza Damghani <[email protected]>
1 parent 35acb0c commit 40f0d37

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16 files changed

+848
-482
lines changed

16 files changed

+848
-482
lines changed

‎vtr_flow/benchmarks/verilog/LU32PEEng.v

100755100644
Lines changed: 103 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -2597,13 +2597,17 @@ module ram (
25972597
output [`RAMWIDTH-1:0] q;
25982598
wire [`RAMWIDTH-1:0] value_out;
25992599
wire [`RAMWIDTH-1:0] subwire;
2600-
assign q = subwire | dummy;
26012600
wire [`RAMWIDTH-1:0] uselessdata;
26022601
assign uselessdata = 1024'b0;
26032602
wire j;
26042603
assign j = |byteena_a;
26052604
wire [`RAMWIDTH-1:0]dummy;
2605+
2606+
assign q = subwire | dummy;
26062607
assign dummy = value_out & 1024'b0;
2608+
2609+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2610+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
26072611
dual_port_ram inst1(
26082612
.clk (clk),
26092613
.we1(wren),
@@ -2637,13 +2641,17 @@ module ram1 (
26372641
output [`RAMWIDTH-1:0] q;
26382642
wire [`RAMWIDTH-1:0] value_out;
26392643
wire [`RAMWIDTH-1:0] subwire;
2640-
assign q = subwire | dummy;
26412644
wire [`RAMWIDTH-1:0] uselessdata;
26422645
assign uselessdata = 1024'b0;
26432646
wire j;
26442647
assign j = |byteena_a;
26452648
wire [`RAMWIDTH-1:0]dummy;
2649+
2650+
assign q = subwire | dummy;
26462651
assign dummy = value_out & 1024'b0;
2652+
2653+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2654+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
26472655
dual_port_ram inst1(
26482656
.clk (clk),
26492657
.we1(wren),
@@ -2677,13 +2685,17 @@ module ram2 (
26772685
output [`RAMWIDTH-1:0] q;
26782686
wire [`RAMWIDTH-1:0] value_out;
26792687
wire [`RAMWIDTH-1:0] subwire;
2680-
assign q = subwire | dummy;
26812688
wire [`RAMWIDTH-1:0] uselessdata;
26822689
assign uselessdata = 1024'b0;
26832690
wire j;
26842691
assign j = |byteena_a;
26852692
wire [`RAMWIDTH-1:0]dummy;
2693+
2694+
assign q = subwire | dummy;
26862695
assign dummy = value_out & 1024'b0;
2696+
2697+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2698+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
26872699
dual_port_ram inst1(
26882700
.clk (clk),
26892701
.we1(wren),
@@ -2717,13 +2729,16 @@ module ram3 (
27172729
output [`RAMWIDTH-1:0] q;
27182730
wire [`RAMWIDTH-1:0] value_out;
27192731
wire [`RAMWIDTH-1:0] subwire;
2720-
assign q = subwire | dummy;
27212732
wire [`RAMWIDTH-1:0] uselessdata;
27222733
assign uselessdata = 1024'b0;
27232734
wire j;
27242735
assign j = |byteena_a;
27252736
wire [`RAMWIDTH-1:0]dummy;
2737+
assign q = subwire | dummy;
27262738
assign dummy = value_out & 1024'b0;
2739+
2740+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2741+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
27272742
dual_port_ram inst1(
27282743
.clk (clk),
27292744
.we1(wren),
@@ -2760,9 +2775,12 @@ module top_ram (
27602775
wire [32-1:0] sub_wire0;
27612776
wire [32-1:0] q;
27622777
wire [32-1:0] junk_output;
2763-
assign q = sub_wire0 | dummy;
27642778
wire[32-1:0] dummy;
2779+
assign q = sub_wire0 | dummy;
27652780
assign dummy = junk_output & 32'b0;
2781+
2782+
defparam inst2.ADDR_WIDTH = 12;
2783+
defparam inst2.DATA_WIDTH = 32;
27662784
dual_port_ram inst2(
27672785
.clk (clk),
27682786
.we1(wren),
@@ -3249,39 +3267,55 @@ if (rdreq)
32493267
counter <= 0;
32503268
else
32513269
counter <= counter + 2'b01;
3252-
if(counter == 0)
3253-
q[`rFIFOINPUTWIDTH-1:0] <= data_ram;
3254-
else if (counter == 1)
3270+
if(counter == 0) begin
3271+
q[`rFIFOINPUTWIDTH-1:0] <= data_ram;
3272+
end
3273+
else if (counter == 1) begin
32553274
q[127:64] <= data_ram;
3256-
else if (counter == 2)
3275+
end
3276+
else if (counter == 2) begin
32573277
q[191:128] <= data_ram;
3258-
else if (counter == 3)
3278+
end
3279+
else if (counter == 3) begin
32593280
q[255:192] <= data_ram;
3260-
else if (counter == 4)
3281+
end
3282+
else if (counter == 4) begin
32613283
q[319:256] <= data_ram;
3262-
else if (counter == 5)
3284+
end
3285+
else if (counter == 5) begin
32633286
q[383:320] <= data_ram;
3264-
else if (counter == 6)
3287+
end
3288+
else if (counter == 6) begin
32653289
q[447:384] <= data_ram;
3266-
else if (counter == 7)
3290+
end
3291+
else if (counter == 7) begin
32673292
q[511:448] <= data_ram;
3268-
else if (counter == 8)
3293+
end
3294+
else if (counter == 8) begin
32693295
q[575:512] <= data_ram;
3270-
else if (counter == 9)
3296+
end
3297+
else if (counter == 9) begin
32713298
q[639:576] <= data_ram;
3272-
else if (counter == 10)
3299+
end
3300+
else if (counter == 10) begin
32733301
q[703:640] <= data_ram;
3274-
else if (counter == 11)
3302+
end
3303+
else if (counter == 11) begin
32753304
q[767:704] <= data_ram;
3276-
else if (counter == 12)
3305+
end
3306+
else if (counter == 12) begin
32773307
q[831:768] <= data_ram;
3278-
else if (counter == 13)
3308+
end
3309+
else if (counter == 13) begin
32793310
q[895:832] <= data_ram;
3280-
else if (counter == 14)
3311+
end
3312+
else if (counter == 14) begin
32813313
q[959:896] <= data_ram;
3282-
else if (counter == 15)
3314+
end
3315+
else if (counter == 15) begin
32833316
q[1023:960] <= data_ram;
32843317
end
3318+
end
32853319
always @ (posedge clk )
32863320
begin // : STATUS_COUNTER
32873321
if ((rdreq) && (!wrreq) && (status_cnt != 0))
@@ -3290,6 +3324,8 @@ begin // : STATUS_COUNTER
32903324
else if ((wrreq) && (!rdreq) && (status_cnt != 64 ))
32913325
status_cnt <= status_cnt + 1'b1;
32923326
end
3327+
defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH;
3328+
defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH;
32933329
dual_port_ram ram_addr(
32943330
.we1 (wrreq) , // write enable
32953331
.we2 (rdreq) , // Read enable
@@ -3353,42 +3389,60 @@ begin //READ_POINTER
33533389
end
33543390
always @ (posedge clk )
33553391
begin //READ_DATA
3356-
if (rdreq)
3392+
if (rdreq) begin
33573393
counter <= 0;
3358-
else
3394+
end
3395+
else begin
33593396
counter <= counter + 2'b01;
3360-
if(counter == 0)
3397+
end
3398+
if(counter == 0) begin
33613399
q <= data_ram[63:0];
3362-
else if(counter == 1)
3400+
end
3401+
else if(counter == 1) begin
33633402
q <= data_ram[127:64];
3364-
else if(counter == 2)
3403+
end
3404+
else if(counter == 2) begin
33653405
q <= data_ram[191:128];
3366-
else if(counter == 3)
3406+
end
3407+
else if(counter == 3) begin
33673408
q <= data_ram[255:192];
3368-
else if(counter == 4)
3409+
end
3410+
else if(counter == 4) begin
33693411
q <= data_ram[319:256];
3370-
else if(counter == 5)
3412+
end
3413+
else if(counter == 5) begin
33713414
q <= data_ram[383:320];
3372-
else if(counter == 6)
3415+
end
3416+
else if(counter == 6) begin
33733417
q <= data_ram[447:384];
3374-
else if(counter == 7)
3418+
end
3419+
else if(counter == 7) begin
33753420
q <= data_ram[511:448];
3376-
else if(counter == 8)
3421+
end
3422+
else if(counter == 8) begin
33773423
q <= data_ram[575:512];
3378-
else if(counter == 9)
3424+
end
3425+
else if(counter == 9) begin
33793426
q <= data_ram[639:576];
3380-
else if(counter == 10)
3427+
end
3428+
else if(counter == 10) begin
33813429
q <= data_ram[703:640];
3382-
else if(counter == 11)
3430+
end
3431+
else if(counter == 11) begin
33833432
q <= data_ram[767:704];
3384-
else if(counter == 12)
3433+
end
3434+
else if(counter == 12) begin
33853435
q <= data_ram[831:768];
3386-
else if(counter == 13)
3436+
end
3437+
else if(counter == 13) begin
33873438
q <= data_ram[895:832];
3388-
else if(counter == 14)
3439+
end
3440+
else if(counter == 14) begin
33893441
q <= data_ram[959:896];
3390-
else if(counter == 15)
3442+
end
3443+
else if(counter == 15) begin
33913444
q <= data_ram[1023:960];
3445+
end
33923446
end
33933447
always @ (posedge clk )
33943448
begin // : STATUS_COUNTER
@@ -3399,6 +3453,9 @@ begin // : STATUS_COUNTER
33993453
status_cnt <= status_cnt + 1'b1;
34003454
end
34013455
assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0];
3456+
3457+
defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH;
3458+
defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH;
34023459
dual_port_ram ram_addr(
34033460
.we1 (wrreq) , // write enable
34043461
.we2 (rdreq) , // Read enable
@@ -3473,6 +3530,9 @@ begin // : STATUS_COUNTER
34733530
else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000))
34743531
status_cnt <= status_cnt + 1;
34753532
end
3533+
3534+
defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH;
3535+
defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH;
34763536
dual_port_ram ram_addr(
34773537
.we1 (wrreq) , // write enable
34783538
.we2 (rdreq) , // Read enable
@@ -3543,6 +3603,8 @@ begin // : STATUS_COUNTER
35433603
else if ((wrreq) && (!rdreq) && (status_cnt != 16 ))
35443604
status_cnt <= status_cnt + 1'b1;
35453605
end
3606+
defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH;
3607+
defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH;
35463608
dual_port_ram ram_addr(
35473609
.we1 (wrreq) , // write enable
35483610
.we2 (rdreq) , // Read enable
@@ -4565,7 +4627,7 @@ module fpmul(clk, a, b, y_out, control, flags) ;
45654627

45664628
flag flager(invalid, overflow, inexact_or_shiftloss,
45674629
shiftloss_or_inexact,
4568-
/* tiny */ stilltiny_or_tiny_and_denormround,
4630+
/* tiny */ still_tiny_or_tiny_and_denormround,
45694631
specialcase, flags);
45704632

45714633

‎vtr_flow/benchmarks/verilog/LU64PEEng.v

100755100644
Lines changed: 27 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3084,6 +3084,9 @@ wire j;
30843084
assign j = |byteena_a;
30853085
wire [`RAMWIDTH-1:0]dummy;
30863086
assign dummy = value_out & 2048'b0;
3087+
3088+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3089+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
30873090
dual_port_ram inst1(
30883091
.clk (clk),
30893092
.we1(wren),
@@ -3124,6 +3127,9 @@ wire j;
31243127
assign j = |byteena_a;
31253128
wire [`RAMWIDTH-1:0]dummy;
31263129
assign dummy = value_out & 2048'b0;
3130+
3131+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3132+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
31273133
dual_port_ram inst1(
31283134
.clk (clk),
31293135
.we1(wren),
@@ -3164,6 +3170,9 @@ wire j;
31643170
assign j = |byteena_a;
31653171
wire [`RAMWIDTH-1:0]dummy;
31663172
assign dummy = value_out & 2048'b0;
3173+
3174+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3175+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
31673176
dual_port_ram inst1(
31683177
.clk (clk),
31693178
.we1(wren),
@@ -3204,6 +3213,9 @@ wire j;
32043213
assign j = |byteena_a;
32053214
wire [`RAMWIDTH-1:0]dummy;
32063215
assign dummy = value_out & 2048'b0;
3216+
3217+
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3218+
defparam inst1.DATA_WIDTH = `RAMWIDTH;
32073219
dual_port_ram inst1(
32083220
.clk (clk),
32093221
.we1(wren),
@@ -3243,6 +3255,9 @@ module top_ram (
32433255
assign q = sub_wire0 | dummy;
32443256
wire[32-1:0] dummy;
32453257
assign dummy = junk_output & 32'b0;
3258+
3259+
defparam inst2.ADDR_WIDTH = 14;
3260+
defparam inst2.DATA_WIDTH = 32;
32463261
dual_port_ram inst2(
32473262
.clk (clk),
32483263
.we1(wren),
@@ -3834,6 +3849,9 @@ begin // : STATUS_COUNTER
38343849
else if ((wrreq) && (!rdreq) && (status_cnt != 64 ))
38353850
status_cnt <= status_cnt + 1'b1;
38363851
end
3852+
3853+
defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH;
3854+
defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH;
38373855
dual_port_ram ram_addr(
38383856
.we1 (wrreq) , // write enable
38393857
.we2 (rdreq) , // Read enable
@@ -3975,6 +3993,9 @@ begin // : STATUS_COUNTER
39753993
status_cnt <= status_cnt + 1'b1;
39763994
end
39773995
assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0];
3996+
3997+
defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH;
3998+
defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH;
39783999
dual_port_ram ram_addr(
39794000
.we1 (wrreq) , // write enable
39804001
.we2 (rdreq) , // Read enable
@@ -4049,6 +4070,9 @@ begin // : STATUS_COUNTER
40494070
else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000))
40504071
status_cnt <= status_cnt + 1;
40514072
end
4073+
4074+
defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH;
4075+
defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH;
40524076
dual_port_ram ram_addr(
40534077
.we1 (wrreq) , // write enable
40544078
.we2 (rdreq) , // Read enable
@@ -4119,6 +4143,8 @@ begin // : STATUS_COUNTER
41194143
else if ((wrreq) && (!rdreq) && (status_cnt != 16 ))
41204144
status_cnt <= status_cnt + 1'b1;
41214145
end
4146+
defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH;
4147+
defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH;
41224148
dual_port_ram ram_addr(
41234149
.we1 (wrreq) , // write enable
41244150
.we2 (rdreq) , // Read enable
@@ -5141,7 +5167,7 @@ module fpmul(clk, a, b, y_out, control, flags) ;
51415167

51425168
flag flager(invalid, overflow, inexact_or_shiftloss,
51435169
shiftloss_or_inexact,
5144-
/* tiny */ stilltiny_or_tiny_and_denormround,
5170+
/* tiny */ still_tiny_or_tiny_and_denormround,
51455171
specialcase, flags);
51465172

51475173

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