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[Infra]: invert yosys+odin changes to vtr_flow/benchmarks
Signed-off-by: Seyed Alireza Damghani <[email protected]>
1 parent 34c3c69 commit 35acb0c

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16 files changed

+2209
-2613
lines changed

16 files changed

+2209
-2613
lines changed

‎vtr_flow/benchmarks/verilog/LU32PEEng.v

100644100755
Lines changed: 148 additions & 245 deletions
Large diffs are not rendered by default.

‎vtr_flow/benchmarks/verilog/LU64PEEng.v

100644100755
Lines changed: 59 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -3084,19 +3084,16 @@ wire j;
30843084
assign j = |byteena_a;
30853085
wire [`RAMWIDTH-1:0]dummy;
30863086
assign dummy = value_out & 2048'b0;
3087-
3088-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3089-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
30903087
dual_port_ram inst1(
3091-
.clk (clk),
3092-
.we1(wren),
3093-
.we2(1'b0),
3094-
.data1(data),
3095-
.data2(uselessdata),
3096-
.out1(value_out),
3097-
.out2(subwire),
3098-
.addr1(wraddress),
3099-
.addr2(rdaddress));
3088+
.clk (clk),
3089+
.we1(wren),
3090+
.we2(1'b0),
3091+
.data1(data),
3092+
.data2(uselessdata),
3093+
.out1(value_out),
3094+
.out2(subwire),
3095+
.addr1(wraddress),
3096+
.addr2(rdaddress));
31003097

31013098

31023099
endmodule
@@ -3127,9 +3124,6 @@ wire j;
31273124
assign j = |byteena_a;
31283125
wire [`RAMWIDTH-1:0]dummy;
31293126
assign dummy = value_out & 2048'b0;
3130-
3131-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3132-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
31333127
dual_port_ram inst1(
31343128
.clk (clk),
31353129
.we1(wren),
@@ -3170,9 +3164,6 @@ wire j;
31703164
assign j = |byteena_a;
31713165
wire [`RAMWIDTH-1:0]dummy;
31723166
assign dummy = value_out & 2048'b0;
3173-
3174-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3175-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
31763167
dual_port_ram inst1(
31773168
.clk (clk),
31783169
.we1(wren),
@@ -3213,9 +3204,6 @@ wire j;
32133204
assign j = |byteena_a;
32143205
wire [`RAMWIDTH-1:0]dummy;
32153206
assign dummy = value_out & 2048'b0;
3216-
3217-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
3218-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
32193207
dual_port_ram inst1(
32203208
.clk (clk),
32213209
.we1(wren),
@@ -3255,19 +3243,16 @@ module top_ram (
32553243
assign q = sub_wire0 | dummy;
32563244
wire[32-1:0] dummy;
32573245
assign dummy = junk_output & 32'b0;
3258-
3259-
defparam inst2.ADDR_WIDTH = 14;
3260-
defparam inst2.DATA_WIDTH = 32;
3261-
dual_port_ram inst2(
3262-
.clk (clk),
3263-
.we1(wren),
3264-
.we2(1'b0),
3265-
.data1(data),
3266-
.data2(data),
3267-
.out1(junk_output),
3268-
.out2(sub_wire0),
3269-
.addr1(wraddress),
3270-
.addr2(rdaddress));
3246+
dual_port_ram inst2(
3247+
.clk (clk),
3248+
.we1(wren),
3249+
.we2(1'b0),
3250+
.data1(data),
3251+
.data2(data),
3252+
.out1(junk_output),
3253+
.out2(sub_wire0),
3254+
.addr1(wraddress),
3255+
.addr2(rdaddress));
32713256

32723257
endmodule
32733258

@@ -3849,19 +3834,16 @@ begin // : STATUS_COUNTER
38493834
else if ((wrreq) && (!rdreq) && (status_cnt != 64 ))
38503835
status_cnt <= status_cnt + 1'b1;
38513836
end
3852-
3853-
defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH;
3854-
defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH;
38553837
dual_port_ram ram_addr(
3856-
.we1 (wrreq) , // write enable
3857-
.we2 (rdreq) , // Read enable
3858-
.addr1 (wr_pointer) , // address_0 input
3859-
.addr2 (rd_pointer) , // address_q input
3860-
.data1 (data) , // data_0 bi-directional
3861-
.data2 (junk_input), // data_1 bi-directional
3862-
.clk(clk),
3863-
.out1 (data_ram),
3864-
.out2 (junk_output)
3838+
.we1 (wrreq) , // write enable
3839+
.we2 (rdreq) , // Read enable
3840+
.addr1 (wr_pointer) , // address_0 input
3841+
.addr2 (rd_pointer) , // address_q input
3842+
.data1 (data) , // data_0 bi-directional
3843+
.data2 (junk_input), // data_1 bi-directional
3844+
.clk(clk),
3845+
.out1 (data_ram),
3846+
.out2 (junk_output)
38653847
);
38663848

38673849

@@ -3993,20 +3975,17 @@ begin // : STATUS_COUNTER
39933975
status_cnt <= status_cnt + 1'b1;
39943976
end
39953977
assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0];
3996-
3997-
defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH;
3998-
defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH;
39993978
dual_port_ram ram_addr(
4000-
.we1 (wrreq) , // write enable
4001-
.we2 (rdreq) , // Read enable
4002-
.addr1 (wr_pointer) , // address_0 input
4003-
.addr2 (rd_pointer) , // address_q input
4004-
.data1 (data) , // data_0 bi-directional
4005-
.data2 (junk_input), // data_1 bi-directional
4006-
.clk(clk),
4007-
.out1 (data_ram),
4008-
.out2 (junk_output)
4009-
);
3979+
.we1 (wrreq) , // write enable
3980+
.we2 (rdreq) , // Read enable
3981+
.addr1 (wr_pointer) , // address_0 input
3982+
.addr2 (rd_pointer) , // address_q input
3983+
.data1 (data) , // data_0 bi-directional
3984+
.data2 (junk_input), // data_1 bi-directional
3985+
.clk(clk),
3986+
.out1 (data_ram),
3987+
.out2 (junk_output)
3988+
);
40103989

40113990

40123991
endmodule
@@ -4070,20 +4049,17 @@ begin // : STATUS_COUNTER
40704049
else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000))
40714050
status_cnt <= status_cnt + 1;
40724051
end
4073-
4074-
defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH;
4075-
defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH;
40764052
dual_port_ram ram_addr(
4077-
.we1 (wrreq) , // write enable
4078-
.we2 (rdreq) , // Read enable
4079-
.addr1 (wr_pointer) , // address_0 input
4080-
.addr2 (rd_pointer) , // address_q input
4081-
.data1 (data) , // data_0 bi-directional
4082-
.data2 (junk_input), // data_1 bi-directional
4083-
.clk(clk),
4084-
.out1 (data_ram),
4085-
.out2 (junk_output)
4086-
);
4053+
.we1 (wrreq) , // write enable
4054+
.we2 (rdreq) , // Read enable
4055+
.addr1 (wr_pointer) , // address_0 input
4056+
.addr2 (rd_pointer) , // address_q input
4057+
.data1 (data) , // data_0 bi-directional
4058+
.data2 (junk_input), // data_1 bi-directional
4059+
.clk(clk),
4060+
.out1 (data_ram),
4061+
.out2 (junk_output)
4062+
);
40874063

40884064

40894065
endmodule
@@ -4143,18 +4119,16 @@ begin // : STATUS_COUNTER
41434119
else if ((wrreq) && (!rdreq) && (status_cnt != 16 ))
41444120
status_cnt <= status_cnt + 1'b1;
41454121
end
4146-
defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH;
4147-
defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH;
41484122
dual_port_ram ram_addr(
4149-
.we1 (wrreq) , // write enable
4150-
.we2 (rdreq) , // Read enable
4151-
.addr1 (wr_pointer) , // address_0 input
4152-
.addr2 (rd_pointer) , // address_q input
4153-
.data1 (data) , // data_0 bi-directional
4154-
.data2 (junk_input), // data_1 bi-directional
4155-
.clk(clk),
4156-
.out1 (data_ram),
4157-
.out2 (junk_output));
4123+
.we1 (wrreq) , // write enable
4124+
.we2 (rdreq) , // Read enable
4125+
.addr1 (wr_pointer) , // address_0 input
4126+
.addr2 (rd_pointer) , // address_q input
4127+
.data1 (data) , // data_0 bi-directional
4128+
.data2 (junk_input), // data_1 bi-directional
4129+
.clk(clk),
4130+
.out1 (data_ram),
4131+
.out2 (junk_output));
41584132

41594133

41604134
endmodule
@@ -5167,7 +5141,7 @@ module fpmul(clk, a, b, y_out, control, flags) ;
51675141

51685142
flag flager(invalid, overflow, inexact_or_shiftloss,
51695143
shiftloss_or_inexact,
5170-
/* tiny */ still_tiny_or_tiny_and_denormround,
5144+
/* tiny */ stilltiny_or_tiny_and_denormround,
51715145
specialcase, flags);
51725146

51735147

@@ -6032,4 +6006,4 @@ module assemble(roundprod, special, y, sign, specialsign,
60326006
(overflow ? overflowvalue[`WIDTH-2:0] :
60336007
rounded[`WIDTH-2:0]);
60346008

6035-
endmodule
6009+
endmodule

‎vtr_flow/benchmarks/verilog/LU8PEEng.v

Lines changed: 30 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -2244,9 +2244,6 @@ wire j;
22442244
assign j = |byteena_a;
22452245
wire [`RAMWIDTH-1:0]dummy;
22462246
assign dummy = value_out & 256'b0;
2247-
2248-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2249-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
22502247
dual_port_ram inst1(
22512248
.clk (clk),
22522249
.we1(wren),
@@ -2287,9 +2284,6 @@ wire j;
22872284
assign j = |byteena_a;
22882285
wire [`RAMWIDTH-1:0]dummy;
22892286
assign dummy = value_out & 256'b0;
2290-
2291-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2292-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
22932287
dual_port_ram inst1(
22942288
.clk (clk),
22952289
.we1(wren),
@@ -2330,9 +2324,6 @@ wire j;
23302324
assign j = |byteena_a;
23312325
wire [`RAMWIDTH-1:0]dummy;
23322326
assign dummy = value_out & 256'b0;
2333-
2334-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2335-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
23362327
dual_port_ram inst1(
23372328
.clk (clk),
23382329
.we1(wren),
@@ -2373,9 +2364,6 @@ wire j;
23732364
assign j = |byteena_a;
23742365
wire [`RAMWIDTH-1:0]dummy;
23752366
assign dummy = value_out & 256'b0;
2376-
2377-
defparam inst1.ADDR_WIDTH = `rRAMSIZEWIDTH;
2378-
defparam inst1.DATA_WIDTH = `RAMWIDTH;
23792367
dual_port_ram inst1(
23802368
.clk (clk),
23812369
.we1(wren),
@@ -2415,9 +2403,6 @@ module top_ram (
24152403
assign q = sub_wire0 | dummy;
24162404
wire[32-1:0] dummy;
24172405
assign dummy = junk_output & 32'b0;
2418-
2419-
defparam inst2.ADDR_WIDTH = 8;
2420-
defparam inst2.DATA_WIDTH = 32;
24212406
dual_port_ram inst2(
24222407
.clk (clk),
24232408
.we1(wren),
@@ -2897,20 +2882,17 @@ begin // : STATUS_COUNTER
28972882
else if ((wrreq) && (!rdreq) && (status_cnt != 64 ))
28982883
status_cnt <= status_cnt + 1'b1;
28992884
end
2900-
2901-
defparam ram_addr.ADDR_WIDTH = `rFIFORSIZEWIDTH;
2902-
defparam ram_addr.DATA_WIDTH = `rFIFOINPUTWIDTH;
29032885
dual_port_ram ram_addr(
2904-
.we1 (wrreq) , // write enable
2905-
.we2 (rdreq) , // Read enable
2906-
.addr1 (wr_pointer) , // address_0 input
2907-
.addr2 (rd_pointer) , // address_q input
2908-
.data1 (data) , // data_0 bi-directional
2909-
.data2 (junk_input), // data_1 bi-directional
2910-
.clk(clk),
2911-
.out1 (data_ram),
2912-
.out2 (junk_output)
2913-
);
2886+
.we1 (wrreq) , // write enable
2887+
.we2 (rdreq) , // Read enable
2888+
.addr1 (wr_pointer) , // address_0 input
2889+
.addr2 (rd_pointer) , // address_q input
2890+
.data1 (data) , // data_0 bi-directional
2891+
.data2 (junk_input), // data_1 bi-directional
2892+
.clk(clk),
2893+
.out1 (data_ram),
2894+
.out2 (junk_output)
2895+
);
29142896

29152897

29162898
endmodule
@@ -2985,20 +2967,17 @@ begin // : STATUS_COUNTER
29852967
status_cnt <= status_cnt + 1'b1;
29862968
end
29872969
assign usedw = status_cnt[`wFIFOSIZEWIDTH-1:0];
2988-
2989-
defparam ram_addr.ADDR_WIDTH = `wFIFOSIZEWIDTH;
2990-
defparam ram_addr.DATA_WIDTH = `wFIFOINPUTWIDTH;
29912970
dual_port_ram ram_addr(
2992-
.we1 (wrreq) , // write enable
2993-
.we2 (rdreq) , // Read enable
2994-
.addr1 (wr_pointer) , // address_0 input
2995-
.addr2 (rd_pointer) , // address_q input
2996-
.data1 (data) , // data_0 bi-directional
2997-
.data2 (junk_input), // data_1 bi-directional
2998-
.clk(clk),
2999-
.out1 (data_ram),
3000-
.out2 (junk_output)
3001-
);
2971+
.we1 (wrreq) , // write enable
2972+
.we2 (rdreq) , // Read enable
2973+
.addr1 (wr_pointer) , // address_0 input
2974+
.addr2 (rd_pointer) , // address_q input
2975+
.data1 (data) , // data_0 bi-directional
2976+
.data2 (junk_input), // data_1 bi-directional
2977+
.clk(clk),
2978+
.out1 (data_ram),
2979+
.out2 (junk_output)
2980+
);
30022981

30032982

30042983
endmodule
@@ -3062,20 +3041,17 @@ begin // : STATUS_COUNTER
30623041
else if ((wrreq) && (!rdreq) && (status_cnt != 5'b10000))
30633042
status_cnt <= status_cnt + 1;
30643043
end
3065-
3066-
defparam ram_addr.ADDR_WIDTH = `aFIFOSIZEWIDTH;
3067-
defparam ram_addr.DATA_WIDTH = `aFIFOWIDTH;
30683044
dual_port_ram ram_addr(
3069-
.we1 (wrreq) , // write enable
3070-
.we2 (rdreq) , // Read enable
3071-
.addr1 (wr_pointer) , // address_0 input
3072-
.addr2 (rd_pointer) , // address_q input
3073-
.data1 (data) , // data_0 bi-directional
3074-
.data2 (junk_input), // data_1 bi-directional
3075-
.clk(clk),
3076-
.out1 (data_ram),
3077-
.out2 (junk_output)
3078-
);
3045+
.we1 (wrreq) , // write enable
3046+
.we2 (rdreq) , // Read enable
3047+
.addr1 (wr_pointer) , // address_0 input
3048+
.addr2 (rd_pointer) , // address_q input
3049+
.data1 (data) , // data_0 bi-directional
3050+
.data2 (junk_input), // data_1 bi-directional
3051+
.clk(clk),
3052+
.out1 (data_ram),
3053+
.out2 (junk_output)
3054+
);
30793055

30803056

30813057
endmodule
@@ -3135,8 +3111,6 @@ begin // : STATUS_COUNTER
31353111
else if ((wrreq) && (!rdreq) && (status_cnt != 16 ))
31363112
status_cnt <= status_cnt + 1'b1;
31373113
end
3138-
defparam ram_addr.ADDR_WIDTH = `mFIFOSIZEWIDTH;
3139-
defparam ram_addr.DATA_WIDTH = `mFIFOWIDTH;
31403114
dual_port_ram ram_addr(
31413115
.we1 (wrreq) , // write enable
31423116
.we2 (rdreq) , // Read enable

‎vtr_flow/benchmarks/verilog/arm_core.v

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5239,7 +5239,7 @@ assign pc_wen = (i_pc_wen || !execute) && !i_conflict;
52395239

52405240
// only update register bank if current instruction executes
52415241
//assign reg_bank_wen = {{15{execute}} & i_reg_bank_wen};
5242-
assign reg_bank_wen = (execute == 1'd1) ? {15'b111111111111111 & i_reg_bank_wen} :
5242+
assign reg_bank_wen = execute ==1'd1? {15'b111111111111111 & i_reg_bank_wen} :
52435243
{15'b0 & i_reg_bank_wen};
52445244

52455245
// ========================================================

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