run make format

Signed-off-by: Alessandro Comodi <[email protected]>

Author: acomodi

libs/libarchfpga/src/arch_util.cpp

@@ -216,7 +216,7 @@ void free_arch(t_arch* arch) {
 }
 
 void free_type_descriptors(std::vector<t_physical_tile_type>& type_descriptors) {
-    for (auto &type : type_descriptors) {
+    for (auto& type : type_descriptors) {
         vtr::free(type.name);
         if (type.index == EMPTY_TYPE_INDEX) {
             continue;
@@ -258,7 +258,7 @@ void free_type_descriptors(std::vector<t_physical_tile_type>& type_descriptors)
 void free_type_descriptors(std::vector<t_logical_block_type>& type_descriptors) {
     free_all_pb_graph_nodes(type_descriptors);
 
-    for (auto &type : type_descriptors) {
+    for (auto& type : type_descriptors) {
         vtr::free(type.name);
         if (type.index == EMPTY_TYPE_INDEX) {
             continue;
@@ -271,7 +271,7 @@ void free_type_descriptors(std::vector<t_logical_block_type>& type_descriptors)
 }
 
 static void free_all_pb_graph_nodes(std::vector<t_logical_block_type>& type_descriptors) {
-    for (auto &type : type_descriptors) {
+    for (auto& type : type_descriptors) {
         if (type.pb_type) {
             if (type.pb_graph_head) {
                 free_pb_graph(type.pb_graph_head);
@@ -1097,7 +1097,7 @@ void CreateModelLibrary(t_arch* arch) {
 
 void SyncModelsPbTypes(t_arch* arch,
                        const std::vector<t_logical_block_type>& Types) {
-    for (auto &Type : Types) {
+    for (auto& Type : Types) {
         if (Type.pb_type != nullptr) {
             SyncModelsPbTypes_rec(arch, Type.pb_type);
         }

libs/libarchfpga/src/echo_arch.cpp

@@ -75,7 +75,7 @@ void EchoArch(const char* EchoFile,
     }
     fprintf(Echo, "*************************************************\n\n");
     fprintf(Echo, "*************************************************\n");
-    for (auto &Type : PhysicalTileTypes) {
+    for (auto& Type : PhysicalTileTypes) {
         fprintf(Echo, "Type: \"%s\"\n", Type.name);
         fprintf(Echo, "\tcapacity: %d\n", Type.capacity);
         fprintf(Echo, "\twidth: %d\n", Type.width);

vpr/src/base/SetupGrid.cpp

@@ -442,7 +442,7 @@ static DeviceGrid build_device_grid(const t_grid_def& grid_def, size_t grid_widt
     }
 
     //Warn if any types were not specified in the grid layout
-    for (auto const &type : device_ctx.physical_tile_types) {
+    for (auto const& type : device_ctx.physical_tile_types) {
         if (&type == empty_type) continue; //Don't worry if empty hasn't been specified
 
         if (!seen_types.count(&type)) {

vpr/src/pack/pack_report.cpp

@@ -17,7 +17,7 @@ void report_packing_pin_usage(std::ostream& os, const VprContext& ctx) {
 
     std::map<t_physical_tile_type_ptr, size_t> total_input_pins;
     std::map<t_physical_tile_type_ptr, size_t> total_output_pins;
-    for (auto const &type : device_ctx.physical_tile_types) {
+    for (auto const& type : device_ctx.physical_tile_types) {
         if (is_empty_type(&type)) continue;
 
         t_pb_type* pb_type = logical_block_type(&type)->pb_type;
@@ -40,7 +40,7 @@ void report_packing_pin_usage(std::ostream& os, const VprContext& ctx) {
 
     os << std::fixed << std::setprecision(2);
 
-    for (auto const &physical_type : device_ctx.physical_tile_types) {
+    for (auto const& physical_type : device_ctx.physical_tile_types) {
         auto type = &physical_type;
         if (is_empty_type(type)) continue;
         if (!inputs_used.count(type)) continue;

vpr/src/pack/pb_type_graph.cpp

@@ -126,7 +126,7 @@ void alloc_and_load_all_pb_graphs(bool load_power_structures) {
     num_edges_head = nullptr;
     auto& device_ctx = g_vpr_ctx.mutable_device();
 
-    for (auto &type : device_ctx.logical_block_types) {
+    for (auto& type : device_ctx.logical_block_types) {
         auto physical_type = &device_ctx.physical_tile_types[type.index];
         if (type.pb_type) {
             type.pb_graph_head = (t_pb_graph_node*)vtr::calloc(1, sizeof(t_pb_graph_node));
@@ -147,7 +147,7 @@ void alloc_and_load_all_pb_graphs(bool load_power_structures) {
         VTR_LOG_ERROR("in pb graph");
         exit(1);
     }
-    for (auto &type : device_ctx.logical_block_types) {
+    for (auto& type : device_ctx.logical_block_types) {
         if (type.pb_type) {
             load_pb_graph_pin_to_pin_annotations(type.pb_graph_head);
         }
@@ -166,7 +166,7 @@ void echo_pb_graph(char* filename) {
     fprintf(fp, "--------------------------------------------\n\n");
 
     auto& device_ctx = g_vpr_ctx.device();
-    for (auto &type : device_ctx.logical_block_types) {
+    for (auto& type : device_ctx.logical_block_types) {
         fprintf(fp, "type %s\n", type.name);
         if (type.pb_graph_head)
             echo_pb_rec(type.pb_graph_head, 1, fp);
@@ -188,7 +188,7 @@ static int check_pb_graph() {
      */
     num_errors = 0;
     auto& device_ctx = g_vpr_ctx.device();
-    for (auto &type : device_ctx.logical_block_types) {
+    for (auto& type : device_ctx.logical_block_types) {
         if (type.pb_type) {
             check_pb_node_rec(type.pb_graph_head);
         }

vpr/src/pack/prepack.cpp

@@ -126,15 +126,15 @@ t_pack_patterns* alloc_and_load_pack_patterns(int* num_packing_patterns) {
 
     /* alloc and initialize array of packing patterns based on architecture complex blocks */
     std::unordered_map<std::string, int> pattern_names;
-    for (auto &type : device_ctx.logical_block_types) {
+    for (auto& type : device_ctx.logical_block_types) {
         discover_pattern_names_in_pb_graph_node(type.pb_graph_head, pattern_names);
     }
 
     list_of_packing_patterns = alloc_and_init_pattern_list_from_hash(pattern_names);
 
     /* load packing patterns by traversing the edges to find edges belonging to pattern */
     for (size_t i = 0; i < pattern_names.size(); i++) {
-        for (auto &type : device_ctx.logical_block_types) {
+        for (auto& type : device_ctx.logical_block_types) {
             // find an edge that belongs to this pattern
             expansion_edge = find_expansion_edge_of_pattern(i, type.pb_graph_head);
             if (!expansion_edge) {
@@ -1173,7 +1173,7 @@ static t_pb_graph_node* get_expected_lowest_cost_primitive_for_atom_block(const
     best_cost = UNDEFINED;
     best = nullptr;
     current = nullptr;
-    for (const auto &type : device_ctx.logical_block_types) {
+    for (const auto& type : device_ctx.logical_block_types) {
         cost = UNDEFINED;
         current = get_expected_lowest_cost_primitive_for_atom_block_in_pb_graph_node(blk_id, type.pb_graph_head, &cost);
         if (cost != UNDEFINED) {

vpr/src/route/rr_graph.cpp

@@ -680,8 +680,8 @@ static void build_rr_graph(const t_graph_type graph_type,
             auto perturb_opins = alloc_and_load_perturb_opins(&types[itype], Fc_out[itype],
                                                               max_chan_width, segment_inf);
             opin_to_track_map[itype] = alloc_and_load_pin_to_track_map(DRIVER,
-                                                                   Fc_out[itype], &types[itype], perturb_opins, directionality,
-                                                                   segment_inf.size(), sets_per_seg_type);
+                                                                       Fc_out[itype], &types[itype], perturb_opins, directionality,
+                                                                       segment_inf.size(), sets_per_seg_type);
         }
     }
     /* END OPIN MAP */

vpr/src/util/vpr_utils.cpp

@@ -718,7 +718,7 @@ void get_pin_range_for_block(const ClusterBlockId blk_id,
 }
 
 t_physical_tile_type_ptr find_block_type_by_name(std::string name, const std::vector<t_physical_tile_type>& types) {
-    for (auto const &type : types) {
+    for (auto const& type : types) {
         if (type.name == name) {
             return &type;
         }
@@ -2228,7 +2228,7 @@ void place_sync_external_block_connections(ClusterBlockId iblk) {
 int max_pins_per_grid_tile() {
     auto& device_ctx = g_vpr_ctx.device();
     int max_pins = 0;
-    for (auto &type : device_ctx.physical_tile_types) {
+    for (auto& type : device_ctx.physical_tile_types) {
         int pins_per_grid_tile = type.num_pins / (type.width * type.height);
         //Use the maximum number of pins normalized by block area
         max_pins = max(max_pins, pins_per_grid_tile);