[Odin]: - update boundtop in Odin-II regression tests

	- regenerate expectation results of techmap_heavysuite
	- remove whitespace changes

Signed-off-by: Seyed Alireza Damghani <[email protected]>

Author: sdamghan

CMakeLists.txt

@@ -393,7 +393,6 @@ elseif(${WITH_ODIN})
     endif()
 endif()
 
-
 #Add extra compilation flags to suppress warnings from some libraries/tools
 # Note that target_compile_options() *appends* to the current compilation options of
 # the specified target

ODIN_II/regression_test/benchmark/task/yosys+odin/large/synthesis_result.json

@@ -58,15 +58,15 @@
         "Latch Drivers": 1,
         "Pi": 273,
         "Po": 193,
-        "logic element": 4141,
-        "latch": 857,
-        "Adder": 136,
+        "logic element": 4204,
+        "latch": 871,
+        "Adder": 151,
         "Memory": 32,
         "generic logic size": 4,
         "Longest Path": 428,
         "Average Path": 4,
-        "Estimated LUTs": 4435,
-        "Total Node": 5167
+        "Estimated LUTs": 4510,
+        "Total Node": 5259
     },
     "large/des_area/k6_frac_N10_frac_chain_mem32K_40nm": {
         "test_name": "large/des_area/k6_frac_N10_frac_chain_mem32K_40nm",

ODIN_II/regression_test/benchmark/task/yosys+odin/vtr/synthesis_result.json

@@ -101,15 +101,15 @@
         "Latch Drivers": 1,
         "Pi": 273,
         "Po": 193,
-        "logic element": 4141,
-        "latch": 857,
-        "Adder": 136,
+        "logic element": 4204,
+        "latch": 871,
+        "Adder": 151,
         "Memory": 32,
         "generic logic size": 4,
         "Longest Path": 428,
         "Average Path": 4,
-        "Estimated LUTs": 4435,
-        "Total Node": 5167
+        "Estimated LUTs": 4510,
+        "Total Node": 5259
     },
     "vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm": {
         "test_name": "vtr/ch_intrinsics/k6_frac_N10_frac_chain_mem32K_40nm",

ODIN_II/regression_test/benchmark/verilog/large/boundtop.v

@@ -222,7 +222,7 @@ wire[63:0] tldata;
         resultinterface ri (t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, resultid, newresult, resultready, resultdata, pglobalreset, tm3_clk_v0); 
         rayinterface rayint (raygroupout, raygroupwe, raygroupid, enablenear, rgData, rgAddr, rgWE, rgAddrValid, rgDone, raydata, rayaddr, raywe, pglobalreset, tm3_clk_v0); 
         boundcontroller  boundcont01(raygroupout01, raygroupwe01, raygroupid01, enablenear01, raygroup01, raygroupvalid01, busy01, triIDvalid01, triID01, wanttriID, reset01, baseaddress01, newresult, BoundNodeID01, resultid, hitmask01, dataready01, empty01, level01, boundnodeIDout01, ack01, lhreset01, addrind01, addrindvalid01, ostdata, ostdatavalid, tladdr01, tladdrvalid01, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_01, t2_01, t3_01, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, id1_01, id2_01, id3_01, hit1_01, hit2_01, hit3_01, bcvalid01, done, cntreset01, passCTS01, passCTS10, pglobalreset, tm3_clk_v0, state01, debugsubcount01, debugcount01);
-        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount01);
+        boundcontroller  boundcont10(raygroupout10, raygroupwe10, raygroupid10, enablenear10, raygroup10, raygroupvalid10, busy10, triIDvalid10, triID10, wanttriID, reset10, baseaddress10, newresult, BoundNodeID10, resultid, hitmask10, dataready10, empty10, level10, boundnodeIDout10, ack10, lhreset10, addrind10, addrindvalid10, ostdata, ostdatavalid, tladdr10, tladdrvalid10, tldata, tldatavalid, t1i, t2i, t3i, u1i, u2i, u3i, v1i, v2i, v3i, id1i, id2i, id3i, hit1i, hit2i, hit3i, t1_10, t2_10, t3_10, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, id1_10, id2_10, id3_10, hit1_10, hit2_10, hit3_10, bcvalid10, done, cntreset10, passCTS10, passCTS01, pglobalreset, tm3_clk_v0, state10, debugsubcount10, debugcount10);
         resulttransmit restransinst (bcvalid01, bcvalid10, id1_01, id2_01, id3_01, id1_10, id2_10, id3_10, hit1_01, hit2_01, hit3_01, hit1_10, hit2_10, hit3_10, u1_01, u2_01, u3_01, v1_01, v2_01, v3_01, u1_10, u2_10, u3_10, v1_10, v2_10, v3_10, rgResultData, rgResultReady, rgResultSource, pglobalreset, tm3_clk_v0); 
 
 assign raygroupout = raygroupout01 | raygroupout10 ;
@@ -287,7 +287,7 @@ assign raygroupout = raygroupout01 | raygroupout10 ;
 
     resultcounter rc (resultid, newresult, done, cntreset, pglobalreset, tm3_clk_v0); 
 
-    // global reset as an output is undriven!
+    // global reset as an output should be driven!
     assign globalreset = pglobalreset;
 
  endmodule
@@ -2821,4 +2821,4 @@ endmodule
           end 
        end 
     end 
- endmodule
+ endmodule

vtr_flow/benchmarks/verilog/arm_core.v

@@ -22,13 +22,13 @@ module single_port_ram_21_8(
     reg 	[`DATA_WIDTH_21_8-1:0] 	RAM[255:0];
 
     always @ (posedge clk) 
-     begin 
-         if (we) 
- 	begin
- 	RAM[addr] <= data;
-         out <= RAM[addr]; 
- 	end
-     end
+    begin 
+        if (we) 
+	begin
+	RAM[addr] <= data;
+        out <= RAM[addr]; 
+	end
+    end 
 
 endmodule
 
@@ -56,14 +56,14 @@ module single_port_ram_128_8(
     reg 	[`DATA_WIDTH_128_8-1:0] 	RAM[255:0];
 
     always @ (posedge clk) 
-     begin 
-         if (we) 
- 	begin
- 	RAM[addr] <= data;
-         out <= RAM[addr]; 
- 	end
-     end
-
+    begin 
+        if (we) 
+	begin
+	RAM[addr] <= data;
+        out <= RAM[addr]; 
+	end
+    end 
+     
 endmodule
 
 
@@ -4048,7 +4048,7 @@ reg  [31:0] r11 = 32'hdeadbeef;
 reg  [31:0] r12 = 32'hdeadbeef;
 reg  [31:0] r13 = 32'hdeadbeef;
 reg  [31:0] r14 = 32'hdeadbeef;
-reg  [23:0] r15; // line: 4272
+reg  [23:0] r15; // see line: 4272
 
 wire  [31:0] r0_out;
 wire  [31:0] r1_out;

vtr_flow/misc/synthesis.ys

@@ -1,8 +1,8 @@
 #################################################################
 # Yosys synthesis script, including generic 'synth' commands, 	#
 # in addition to techmap asynchronous FFs and VTR hard blocks.	#
-# Once the VTR flow runs with Yosys front-end, Yosys synthesize	#
-# the input design using the following commands. 				#
+# Once the VTR flow runs with the Yosys front-end, Yosys        #
+# synthesizes the input design using the following commands. 	#
 #																#
 # NOTE: the script is adapted from the one Eddie Hung proposed 	#
 # for VTR-to-Bitstream[1]. However, a few minor changes to make	#